3D IC testing apparatus

• US 8,922,230 B2
• Filed: 05/11/2011
• Issued: 12/30/2014
• Est. Priority Date: 05/11/2011
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Mill-Jer, Chen, Chih-Chia, Lin, Hung-Chih, Peng, Ching-Nen, Chen, Hao
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US13/105,603
• Publication Number:
  US 20120286814A1
• Time in Patent Office: 1,329 Days
• Field of Search: None
• US Class Current: 324/754.03
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: Y02P 80/30 Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

A three dimensional (3D) integrated circuit (IC) testing apparatus includes a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that an electrical characteristic test of the variety of TSVs can be tested all at once.

Claims

1. An apparatus comprising:

a testing setup having a plurality of probes configured to be aligned with a plurality of through-silicon vias (TSVs) of a device under test, wherein a bottom terminal of the probe is thinner than a remaining portion of the probe; and

a plurality of conductive devices, each of which connects two adjacent probes, wherein the plurality of conductive devices and the plurality of probes form a conductive chain through a removable contact between the probe and the device under test when the device under test is placed within the apparatus.

2. The apparatus of claim 1, further comprising:

a first terminal of a first probe configured to align and electrically connect with a first TSV having a top terminal;

a first terminal of a second probe configured to align and electrically connect with a second TSV having a top terminal;

a first conductive device coupled between a second terminal of the first probe and a second terminal of the second probe; and

a second conductive device configured to electrically connect with a bottom terminal of a third TSV and a bottom terminal of the second TSV.

3. The apparatus of claim 1, wherein the testing setup is a probe card comprising:

the plurality of probes, each of which is configured to align and connect to a corresponding bump formed on top of the TSV.

4. The apparatus of claim 1, wherein the plurality of conductive devices comprises:

a first group of conductive devices located in a probe card having the plurality of probes configured to align and connect to the plurality of TSVs; and

a second group of conductive devices located in a plurality of dummy dies, each of which is configured to connect the plurality of TSVs.

5. The apparatus of claim 1, wherein the testing setup is an automatic testing equipment (ATE) board comprising:

the plurality of conductive devices, each of which connects two adjacent probes of a probe card through a conductive medium.

6. The apparatus of claim 1, further comprising a three-dimensional (3D) die comprising a plurality of TSVs, each of which has a first terminal coupled to a flip chip bump and a second terminal coupled to a micro bump.

7. The apparatus of claim 1, further comprising an interposer comprising:

a plurality of TSVs having a first terminal connected to the testing setup through a first group of bumps formed on a first side of the interposer and a second terminal connected to a second side of the interposer through a second group of bumps formed on the second side of the interposer; and

a plurality of conductive elements formed on second side of the interposer, wherein each of the plurality of the conductive elements connects two adjacent TSVs.

8. A system comprising:

a plurality of through-silicon vias (TSVs); and

a testing apparatus comprising;

a testing setup having a plurality of probes aligned with the plurality of through-silicon vias (TSVs), wherein a bottom terminal of the probe is thinner than a remaining portion of the probe; and

a plurality of conductive devices, each of which connects two adjacent probes, wherein the plurality of conductive devices, the plurality of probes and the plurality of TSVs form a conductive chain through a removable connection between the probe and a corresponding TSV.

9. The system of claim 8, further comprising:

a plurality of dummy dies coupled to the plurality of TSVs, wherein a plurality of conductive paths formed on the dummy dies are configured such that;

the plurality of TSVs, the plurality of conductive paths and the plurality of conductive devices form the conductive chain.

10. The system of claim 9, wherein the plurality of dummy dies comprise 3D dies and 2.5D dies.

11. The system of claim 8, further comprising:

a plurality of testing modules configured to test resistance, capacitance and leakage current of the plurality of TSVs.

12. The system of claim 8, wherein the testing apparatus is an ATE testing board coupled to the plurality of TSVs through a probe card.

13. The system of claim 8, wherein the testing apparatus is a probe card having the plurality of probes coupled to the plurality of TSVs.

14. The system of claim 8, wherein the plurality of TSVs, the testing apparatus are configured such that:

the conductive chain has a first terminal receiving a testing signal and a second terminal generating a result signal comprising electrical characteristics of the plurality of TSVs.