Methods and apparatus for clock tree phase alignment

• US 8,922,264 B1
• Filed: 04/26/2013
• Issued: 12/30/2014
• Est. Priority Date: 04/26/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chong, Yan, Nordyke, Warren, Lu, Sean Shau-Tu, Ding, Weiqi
• Primary Examiner(s): LUU, AN T
• Application Number:
  US13/871,812
• Time in Patent Office: 613 Days
• Field of Search: 327/231, 327/235, 327/236, 327/355, 327/356, 327/361, 327/291, 327/293, 327/298, 375/329, 375/332, 375334-335
• US Class Current: 327/291
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

Clock alignment circuitry may include phase comparator circuitry with a first input terminal that receives as first clock signal from a first clock tree and a second input terminal that receives a second clock signal from a second clock tree. The phase comparator circuitry may compare the first and second clock signals and generate different control signals based on the first and second clock signals. The integrated circuit may further include phase interpolator circuitry that generates an output clock signal based on at least one of the control signals received from the phase comparator circuitry. Edges of the generated output clock signal may align with edges of either the first clock signal or the second clock signal.

Claims

1. Clock alignment circuitry comprising:

phase comparator circuitry having a first input terminal that receives a first clock signal from a first clock tree and a second input terminal that receives a second clock signal from a second clock tree, wherein the phase comparator circuitry compares the first and second clock signals and outputs corresponding first and second control signals; and

phase interpolator circuitry that receives a third clock signal and that generates an output clock signal that is aligned with one of the first and second clock signals based on at least one of the first and second control signals, wherein the first clock signal comprises a loopback version of the third clock signal being routed through the first clock tree.

2. The clock alignment circuitry defined in claim 1, wherein the phase comparator circuitry operates at a first frequency, wherein the phase interpolator circuitry operates at a second frequency, and wherein the phase comparator circuitry comprises:

a two-phase detector circuit that receives the first and second clock signals, wherein the two-phase detector circuit produces first and second output signals based on phases of the first and second clock signals; and

synchronization circuitry having first and second input terminals that receives the first and second output signals, respectively, wherein the synchronization circuitry asserts the first control signal when the first output signal switches from one logic level to another, and wherein the synchronization circuitry asserts the second control signal when the second output signal switches from one logic level to another.

3. The clock alignment circuitry defined in claim 2, wherein the synchronization circuitry comprises:

a first logic circuit that receives the first and second output signals from the phase detector circuit;

first and second storage elements each having a clock terminal that receives the second clock signal, wherein the first and second storage elements produce the first and second control signals, respectively;

a second logic circuit having a first input terminal that receives an output from the first logic circuit and a second input terminal that receives the first control signal as a feedback input; and

a third logic circuit having a first input terminal that receives the first output signal from the phase detector circuit and a second input terminal that receives the second control signal as a feedback input.

4. The clock alignment circuitry defined in claim 2, wherein the two-phase detector circuit comprises:

a first phase detector that receives a delayed version of the first clock signal and the second clock signal, wherein the first phase detector produces the first output signal based on phases of the delayed version of the first clock signal and the second clock signal; and

a second phase detector that receives the delayed version of the first clock signal and a delayed version of the second clock signal, wherein the second phase detector produces the second output signal based on phases of the delayed versions of the first and second clock signals.

5. The clock alignment circuitry defined in claim 4, wherein the two-phase detector circuit further comprises:

a first delay chain that receives the first clock signal to produce the delayed version of the first clock signal; and

a second delay chain that receives the second clock signal to produce the delayed version of the second clock signal, wherein the second delay chain has a longer delay than the first delay chain.

6. The clock alignment circuitry defined in claim 5, wherein the second clock signal comprises a first sampling window for the first phase detector circuit, wherein the delayed version of the second clock signal comprises a second sampling window for the second phase detector circuit, and wherein the second sampling window comes after the first sampling window.

7. The clock alignment circuitry defined in claim 1, wherein the phase interpolator circuitry comprises:

an adder circuit that receives a plurality of bits as a step value based on at least one of the first and second control signals, wherein the adder circuit generates a plurality of select bits based on an accumulated step value; and

a phase interpolator circuit that receives at least three different respective phases of the third clock signal, wherein the phase interpolator outputs an interpolated clock signal from the three different respective phases of the third clock signal based on the plurality of select bits.

8. The clock alignment circuitry defined in claim 7, wherein the phase interpolator circuitry further comprises:

an additional phase interpolator circuit that receives at least an additional three different respective phases of the third clock signal, the additional phase interpolator having an output that generates an additional interpolated clock signal from the additional three different respective phases of the third clock signal based on the plurality of select bits; and

clock divider circuitry that receives the interpolated clock signal and the additional interpolated clock signal, wherein the clock divider circuitry generates the adjusted output clock signal based on the interpolated and the additional interpolated clock signals.

9. The clock alignment circuitry defined in claim 8, wherein the third clock signal is an eight-phase clock signal, wherein the three respective phases of the third clock signal are three neighboring phases in the eight-phase clock signal, and wherein the additional three respective phases are opposite phases of the three respective phases.

10. Clock alignment circuitry comprising:

phase comparator circuitry that receives first and second feedback clock signals from first and second clock trees, respectively, wherein the phase comparator circuitry generates first and second control signals based on phases of the first and second feedback clock signals; and

phase interpolator circuitry that receives the first and second control signals and that adjusts a phase of an output feedback clock signal based on at least one of the first and second control signals such that the phase of the output feedback clock signal is aligned with a phase of the first feedback clock signal, wherein the phase interpolator circuitry comprises;

a first phase interpolator that receives first, second, and third phases of an input clock signal and that generates a corresponding first interpolated clock signal; and

a second phase interpolator that receives fourth, fifth and sixth phases of the input clock signal and that generates a corresponding second interpolated clock signal, wherein the first, second, third, fourth, fifth, and sixth clock phases each have a different respective phase value, and wherein the first feedback clock signal comprises a feedback of the input clock signal.

11. The clock alignment circuitry defined in claim 10, further comprising:

a clock divider circuit that receives the first and second interpolated clock signals, wherein the clock divider circuit generates the output feedback clock signal based on the first and second interpolated clock signals.

12. The clock alignment circuitry defined in claim 10, further comprising:

a plurality of multiplexing circuits that receives a plurality of phases of the input clock signal, wherein first, second, and third multiplexing circuits in the plurality of multiplexing circuits selectively transmits the respective first, second and third phases of the input clock signal to the first phase interpolator, and wherein fourth, fifth and sixth multiplexing circuits in the plurality of multiplexing circuits selectively transmits the respective fourth, fifth and sixth phases of the input clock signal to the second phase interpolator.

13. The clock alignment circuitry defined in claim 10, wherein the first and second interpolators further receives a plurality of select bits, and wherein the first and second interpolated clock signals are generated based on the plurality of select bits.

14. The clock alignment circuitry defined in claim 13 further comprising:

an adder circuit that receives an input signal with a selected predefined value, wherein the adder circuit generates the plurality of select bits based on an accumulated selected predefined value.

15. The clock alignment circuitry defined in claim 14 further comprising:

a selector circuit that receives a plurality of input signals with respective predefined values, wherein the selector circuit further receives the first and second control signals from the phase comparator circuitry, wherein an output of the selector circuit transmits one of the input signals to the adder circuit as the input signal with the selected predefined value based on the first and second control signals from the phase comparator circuitry.

16. A method of aligning clock signals in an integrated circuit, the method comprising:

with phase comparator circuitry, comparing a first feedback clock signal received from a first clock tree with a second feedback clock signal received from a second clock tree;

in response to comparison of the first and second feedback clock signals, generating first and second control signals with the phase comparator circuitry; and

with interpolator circuitry, interpolating from a plurality of phases of a third clock signal based on at least one of the first and second control signals to generate an output clock signal, wherein the third clock signal is routed through the first clock tree to produce the first feedback clock signal.

17. The method defined in claim 16 further comprising:

generating a plurality of select bits based on the first and second control signals; and

with a selection circuit, selecting at least three neighboring phases of the third clock signal based on a first portion of the plurality of select bits, wherein the interpolation is performed among the three neighboring phases based on a second portion of the plurality of select bits.

18. The method defined in claim 17, wherein the first and second feedback clock signals have a first frequency and wherein the third clock signal has a second frequency, the method further comprising:

with a clock divider circuit, dividing the output clock signal to generate an aligned output clock signal, wherein the aligned output clock signal is an adjusted version of the first feedback clock signal with edges that align with edges of the second feedback clock signal.

19. The method defined in claim 16, wherein generating the first and second control signals in response to the comparison comprises:

with a first delay chain, delaying the first feedback clock signal to generate a delayed version of the first feedback clock signal;

with a second delay chain that is longer than the first delay chain, delaying the second feedback clock signal to generate a delayed version of the second feedback clock signal;

with a first phase detector circuit in the phase comparator circuitry, comparing the delayed version of the first feedback clock signal with the second feedback clock signal to generate a first output signal; and

with a second phase detector circuit in the phase comparator circuitry, comparing the delayed versions of the first and second feedback clock signals to generate a second output signal, wherein the first and second control signals are generated based on the first and second output signals.