Self-referenced sense amplifier for spin torque MRAM

• US 8,923,041 B2
• Filed: 03/15/2013
• Issued: 12/30/2014
• Est. Priority Date: 04/11/2012
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Everspin Technologies Incorporated
• Inventors: Andre, Thomas, Alam, Syed M., Subramanian, Chitra
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US13/835,426
• Publication Number:
  US 20130272060A1
• Time in Patent Office: 655 Days
• Field of Search: 365/158, 365/173
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.

Claims

1. A method of reading data from each of a plurality of memory cells in a spin torque magnetoresistive memory array, the method comprising:

applying a read voltage across a source line and a bit line coupled to a memory cell;

applying a write current in a first direction through the memory cell to write a first state;

reapplying the read voltage across the source line and the bit line; and

applying a programmable offset current to the one of the bit line or the source line, wherein the programmable offset current is applied during, but after initiation of, the reapplying step.

2. The method of claim 1, wherein the programmable offset current is applied during, but after a programmable delay from the initiation of, the reapplying step.

3. The method of claim 1, wherein magnitude of the programmable offset current is half of a difference between a read current through the memory cell when applying the read voltage to a memory cell in the first state and applying the read voltage to a memory cell in a second state.

4. The method of claim 1, wherein the memory cell has a resistance range, the method further comprising:

setting a read voltage magnitude based on an applied voltage to a high or low end of the resistance range.

5. The method of claim 1, wherein the reapplying the read voltage further comprises:

reapplying a source line voltage at a first end of the source line using a first PMOS follower circuitry and at a second end of the source line using a second PMOS follower circuitry; and

reapplying a bit line voltage to at least one end of a bit line using a preamplifier circuitry, the bit line voltage of a higher magnitude than the source line voltage by at least the read voltage.

6. The method of claim 1, further comprising:

isolating a first bias voltage associated with the programmable offset current prior to applying the read voltage.

7. The method of claim 1, wherein the applying a read voltage further comprises:

applying a source line voltage at a first end of the source line using a first PMOS follower circuitry and at a second end of the source line using a second PMOS follower circuitry; and

applying a bit line voltage to at least one end of a bit line using a preamplifier circuitry, the bit line voltage of a higher magnitude than the source line voltage by at least the read voltage.

8. The method of claim 7, further comprising:

providing a first bias voltage for the first PMOS follower circuitry and the second PMOS follower circuitry;

providing a second bias voltage for the preamplifier circuitry; and

isolating the first and second bias voltages from first and second voltage supplies, respectively, prior to the applying the read voltage across the source line and the bit line coupled to the memory cell.

9. The method of claim 8, further comprising:

coupling the first bias voltage with the second bias voltage by a capacitor.

10. A method of reading data from each of a plurality of memory cells in a spin torque magnetoresistive memory array, the method comprising:

applying a read voltage across a magnetic tunnel junction within a memory cell;

converting a current through the magnetic tunnel junction under the applied read voltage into a sample voltage;

storing the sample voltage in a capacitor;

applying a first write current through the magnetic tunnel junction to reset the memory cell to a first state;

reapplying the read voltage across the magnetic tunnel junction;

using the sample voltage and a programmable offset current to create a reference current;

converting a difference between the reference current and the current through the magnetic tunnel junction under the reapplied read voltage to generate an evaluation voltage; and

comparing the sample voltage and the evaluation voltage.

11. The method of claim 10, further comprising:

selectively applying a second write current through the magnetic tunnel junction to set the memory cell to a second state in response to the comparing of the sample voltage and the evaluation voltage.

12. The method of claim 10, wherein the programmable offset current is applied during, but after initiation of, the reapplying step.

13. The method of claim 10, wherein the programmable offset current is applied during, but after a programmable delay from the initiation of, the reapplying step.

14. The method of claim 10, wherein magnitude of the programmable offset current is half of a difference between a read current through the memory cell when applying the read voltage to a memory cell in the first state and applying the read voltage to a memory cell in a second state.

15. The method of claim 10, wherein the memory cell has a resistance range, the method further comprising:

setting a read voltage magnitude based on an applied voltage to a high or low end of the resistance range.

16. The method of claim 10, wherein the reapplying the read voltage further comprises:

applying a source line voltage at a first end of a source line using a first PMOS follower circuitry and at a second end of the source line using a second PMOS follower circuitry; and

applying a bit line voltage to at least one end of a bit line using a preamplifier circuitry, the bit line voltage of a higher magnitude than the source line voltage by at least the read voltage.

17. The method of claim 10, further comprising:

isolating a first bias voltage associated with the programmable offset current prior to applying the read voltage.

18. The method of claim 10, wherein the applying a read voltage further comprises:

applying a source line voltage at a first end of a source line using a first PMOS follower circuitry and at a second end of the source line using a second PMOS follower circuitry; and

applying a bit line voltage to at least one end of a bit line using a preamplifier circuitry, the bit line voltage of a higher magnitude than the source line voltage by at least the read voltage.

19. The method of claim 18, further comprising:

providing a first bias voltage for the first PMOS follower circuitry and the second PMOS follower circuitry;

providing a second bias voltage for the preamplifier circuitry; and

isolating the first and second bias voltages from first and second voltage supplies, respectively, prior to applying the read voltage across the magnetic tunnel junction.

20. The method of claim 19, further comprising:

coupling the first bias voltage with the second bias voltage by a capacitor.

21. A spin torque magnetoresistive memory array having a plurality of memory cells, each memory cell of the plurality of memory cells selectively coupled between a respective bit line of a plurality of bit lines and a respective source line of a plurality of source lines, the spin torque magnetoresistive memory array comprising:

column selection circuitry coupled to first and second ends of each source line of the plurality of source lines and to a first end of each bit line of the plurality of bit lines and configured to select a specific bit line of the plurality of bit lines;

global bias circuitry configured to provide a plurality of timed bias voltages;

sense amplifiers and write drivers coupled between the column selection circuitry and the global bias circuitry, the sense amplifiers and write drivers configured to;

receive the timed bias voltages; and

for a memory cell coupled to the specific bit line;

apply a read voltage across the source line and the specific bit line coupled to the memory cell;

apply a write current in a first direction through the memory cell to write a first state;

reapply the read voltage across the source line and the specific bit line coupled to the memory cell; and

apply a programmable offset current to the specific bit line.

22. The spin torque magnetoresistive memory array of claim 21, wherein the sense amplifiers and write drivers comprise PMOS-follower circuitry coupled to one of the source line and the specific bit line coupled to the memory cell and configured to regulate a voltage thereupon.

23. The spin torque magnetoresistive memory array of claim 21, wherein the sense amplifiers and write drivers comprise PMOS-follower circuitry coupled to the source line coupled to the memory cell and configured to regulate a voltage at first and second ends of the source line.