Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating

• US 8,923,052 B2
• Filed: 08/02/2011
• Issued: 12/30/2014
• Est. Priority Date: 04/08/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US13/196,471
• Publication Number:
  US 20110305085A1
• Time in Patent Office: 1,246 Days
• Field of Search: 365/185.03, 365/185.08, 365/185.16
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, and a control gate positioned above the trapping layer.

Claims

1. A semiconductor memory cell comprising:

a substrate having a first conductivity type;

a first region embedded in the substrate at a first location of the substrate and having a second conductivity type;

a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory;

a trapping layer positioned in between the first and second locations and above a surface of the substrate;

the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and

a control gate positioned above the trapping layer,

wherein said cell is configured so that one of said first and second storage locations interacts with said floating body so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body.

2. The semiconductor memory cell of claim 1, wherein only one of said first and second storage locations is configured to receive transfer of data stored by the volatile memory upon interruption of power to the memory cell.

3. The semiconductor memory cell of claim 1, wherein the first conductivity type is “

p”

type and the second conductivity type is “

n”

type.

4. The semiconductor memory cell of claim 1, further comprising insulating layers bounding the side surfaces of the substrate.

5. The semiconductor memory cell of claim 1, wherein said volatile data stored in said floating body determines said non-volatile data stored in one of said first and second storage locations.

6. The semiconductor memory cell of claim 1, wherein said cell functions as a multi-level cell.

7. The semiconductor memory cell of claim 6, wherein at least one of said first and second storage locations is configured so that more than one bit of data can be stored in said at least one of said first and second storage locations, respectively.

19. The semiconductor memory cell of claim 1, further comprising a buried insulator layer bounding a bottom of said floating body.

8. A semiconductor memory cell comprising:

a substrate having a first conductivity type;

a first region embedded in the substrate at a first location of the substrate and having a second conductivity type;

a second region embedded in the substrate at a second location of the substrate and having the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory;

a buried insulator layer bounding a bottom of said floating body;

a trapping layer positioned in between the first and second locations and above a surface of the substrate;

the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and

a control gate positioned above the trapping layer;

wherein said cell is configured so that one of said first and second storage locations interacts with said floating body so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body.

9. The semiconductor memory cell of claim 8, wherein said first and second regions bound sides of said floating body.

10. The semiconductor memory cell of claim 8, further comprising insulating layers bounding side surfaces of the substrate.

11. The semiconductor memory cell of claim 8, wherein the first conductivity type is “

p”

type and the second conductivity type is “

n”

type.

12. The semiconductor memory cell of claim 8, wherein said cell functions as a multi-level cell.

13. The semiconductor memory cell of claim 12, wherein at least one of said first and second storage locations is configured so that more than one bit of data can be stored in said at least one of said first and second storage locations, respectively.

14. A memory array comprising a plurality of rows and columns of semiconductor memory cells, a plurality of said cells each comprising:

a floating body region to store charge as volatile memory;

first and second regions;

a trapping layer positioned in between the first and second locations and above a surface of the substrate;

the trapping layer comprising first and second storage locations being configured to store charge as nonvolatile memory independently of one another;

a control gate positioned above the trapping layer; and

control terminals defining the columns of said memory array are electrically connected to said first and second regions;

wherein said cell is configured so that one of said first and second storage locations interacts with said floating body so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body.

15. The memory array of claim 14, further comprising control terminals electrically connecting the rows of said memory array, respectively, to said control gate.

16. The memory array of claim 14, wherein said plurality of memory cells each comprise a buried layer, electrically connected to an additional control terminal that is shared among at least two of said plurality of memory cells.

17. The memory array of claim 14, wherein the number of said control terminals defining the columns is equal to twice the number of the columns.

18. The memory array of claim 14, wherein the number of said control terminals defining the columns is equal to the number of the column plus one.