Memory circuit, memory unit, and signal processing circuit

• US 8,923,076 B2
• Filed: 01/07/2014
• Issued: 12/30/2014
• Est. Priority Date: 03/31/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/148,920
• Publication Number:
  US 20140126272A1
• Time in Patent Office: 357 Days
• Field of Search: 365/189.05, 365/189.03, 365/189.08, 365/149
• US Class Current: 365/189.05
• CPC Class Codes: G11C 16/045 Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H01L 27/06 including a plurality of individual components in a non-repetitive configuration
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Abstract

A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit.

Claims

1. A memory circuit comprising:

a transistor;

a capacitor;

a first arithmetic circuit;

a second arithmetic circuit;

a third arithmetic circuit; and

a switch,

wherein an output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit,

wherein an output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit,

wherein the input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor,

wherein the other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit,

wherein an output terminal of the third arithmetic circuit is electrically connected to the input terminal of the first arithmetic circuit via the switch, and

wherein the transistor comprises an oxide semiconductor layer.

2. The memory circuit according to claim 1, wherein each of the first arithmetic circuit, the second arithmetic circuit, the third arithmetic circuit and the switch comprises a transistor including a semiconductor other than an oxide semiconductor.

3. The memory circuit according to claim 1, wherein the switch comprises a transistor comprising a channel formation region formed in single crystal silicon.

4. The memory circuit according to claim 1, wherein the switch comprises a transistor having higher mobility than the transistor comprising the oxide semiconductor layer.

5. The memory circuit according to claim 1, wherein each of the first arithmetic circuit, the second arithmetic circuit and the third arithmetic circuit is any one of an inverter, a three-state buffer, a clocked inverter, a NAND circuit and a NOR circuit.

6. A memory unit comprising the memory circuit according to claim 1.

7. A signal processing circuit comprising:

a CPU;

a memory; and

a peripheral control unit for controlling access between the memory and the CPU,

wherein the CPU, the memory, and the peripheral control unit each include the memory circuit according to claim 1.

8. A memory circuit comprising:

a flip-flop circuit comprising a first node, a second node, a first arithmetic circuit and a second arithmetic circuit;

a transistor;

a capacitor;

a third arithmetic circuit; and

a switch,

wherein while a supply voltage is supplied, a signal at the second node is an inverted signal of a signal at the first node,

wherein one of a source and a drain of the transistor is electrically connected to the first node,

wherein the other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit,

wherein an output terminal of the third arithmetic circuit is electrically connected to the first node via the switch, and

wherein the transistor comprises an oxide semiconductor layer.

9. The memory circuit according to claim 8, wherein each of the flip-flop circuit and the switch comprises a transistor including a semiconductor other than an oxide semiconductor.

10. The memory circuit according to claim 8, wherein the switch comprises a transistor comprising a channel formation region formed in single crystal silicon.

11. The memory circuit according to claim 8, wherein the switch comprises a transistor having higher mobility than the transistor comprising the oxide semiconductor layer.

12. The memory circuit according to claim 8, wherein each of the first arithmetic circuit, the second arithmetic circuit and the third arithmetic circuit is any one of an inverter, a three-state buffer, a clocked inverter, a NAND circuit and a NOR circuit.

13. A memory unit comprising the memory circuit according to claim 8.

14. A signal processing circuit comprising:

a CPU;

a memory; and

a peripheral control unit for controlling access between the memory and the CPU,

wherein the CPU, the memory, and the peripheral control unit each include the memory circuit according to claim 8.