Method and system for an integrated dual port gigabit ethernet controller chip
First Claim
1. A method for processing network data, the method comprising:
- receiving, by an integrated chip comprising first and second Ethernet controllers, a first request to access said first Ethernet controller from a first host process and a second request to access said first Ethernet controller from a second host process, the first and second host processes running on a host system external to the integrated chip;
arbitrating, by an arbiter of said integrated chip, which one of said first and second requests is granted access to said first Ethernet controller;
acknowledging, by said integrated chip, access to one of said first and second host processes based on said arbitrating; and
after transmitting said acknowledgment, facilitating, by said arbiter, transfer of data between said one of said first and second host processes running on the host system and a network via said first Ethernet controller.
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Accused Products
Abstract
Aspects of the invention may include a dual port Ethernet controller having a bus interface, a first Ethernet controller coupled to the bus interface such as a PCI bus interface and a second Ethernet controller coupled to the bus interface. The first Ethernet controller, second Ethernet controller and bus interface are integrated within a single chip. The dual port Ethernet controller may also include an arbiter, which is coupled to the first Ethernet controller, the second Ethernet controller and the bus interface. A plurality of shared resources may be coupled to one or more of the first Ethernet controller, the second Ethernet controller and the arbiter. The shared resources may include, but is not limited to, a non-volatile memory 304 and a general purpose input/out interface.
25 Citations
24 Claims
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1. A method for processing network data, the method comprising:
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receiving, by an integrated chip comprising first and second Ethernet controllers, a first request to access said first Ethernet controller from a first host process and a second request to access said first Ethernet controller from a second host process, the first and second host processes running on a host system external to the integrated chip; arbitrating, by an arbiter of said integrated chip, which one of said first and second requests is granted access to said first Ethernet controller; acknowledging, by said integrated chip, access to one of said first and second host processes based on said arbitrating; and after transmitting said acknowledgment, facilitating, by said arbiter, transfer of data between said one of said first and second host processes running on the host system and a network via said first Ethernet controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A dual port Ethernet controller;
- comprising;
a bus interface; a first Ethernet controller coupled to said bus interface; a second Ethernet controller coupled to said bus interface, said bus interface, said first Ethernet controller, and said second Ethernet controller being integrated within a single chip; and an arbiter configured to receive, via said bus interface, a first request to access said first Ethernet controller from a first host process and a second request to access said first Ethernet controller from a second host process, the first and second host processes running on a host system external to the integrated chip, arbitrate which one of said first and second requests is granted access to said first Ethernet controller, and acknowledge access to one of said first and second host processes running on the host system based on said arbitrating. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
- comprising;
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24. A dual port Ethernet controller comprising:
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a bus interface; a first Ethernet controller coupled to said bus interface; a second Ethernet controller coupled to said bus interface, said bus interface, said first Ethernet controller, and said second Ethernet controller being integrated within a single chip; an arbiter configured to receive, via said bus interface, a first request to access said first Ethernet controller from a first host process and a second request to access said first Ethernet controller from a second host process, arbitrate which one of said first and second requests is granted access to said first Ethernet controller, and acknowledge access to one of said first and second host processes based on said arbitrating; and at least one debug interface integrated within said single chip and coupled to at least one of said bus interface, said first Ethernet controller, and said second Ethernet controller, wherein said at least one debug interface comprises a JTAG interface.
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Specification