Pulse signal output circuit and shift register

• US 8,923,471 B2
• Filed: 01/31/2013
• Issued: 12/30/2014
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyake, Hiroyuki
• Primary Examiner(s): Lam, Tuan T
• Application Number:
  US13/754,959
• Publication Number:
  US 20130135023A1
• Time in Patent Office: 698 Days
• Field of Search: None
• US Class Current: 377/64
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit are provided. A clock signal is supplied to one of transistors connected to a first output terminal. A power supply potential is applied to one of transistors connected to a second output terminal. Thus, power consumed by discharge and charge of the transistor included in the second output terminal can be reduced. Further, since a potential is supplied from a power source to the second output terminal, sufficient charge capability can be obtained.

Claims

1. A shift register comprising:

a first wiring;

a second wiring;

a third wiring; and

a pulse signal output circuit electrically connected to the first, second, and third wirings, comprising;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a first input signal generation circuit; and

a second input signal generation circuit,

wherein a first terminal of the first transistor and a first terminal of the second transistor are electrically connected to each other to function as a first output terminal,

wherein a first terminal of the third transistor and a first terminal of the fourth transistor are electrically connected to each other to function as a second output terminal,

wherein a gate terminal of the first transistor, a gate terminal of the third transistor, and an output terminal of the first input signal generation circuit are electrically connected to each other,

wherein a gate terminal of the second transistor, a gate terminal of the fourth transistor, and an output terminal of the second input signal generation circuit are electrically connected to each other,

wherein a first clock signal is input to a second terminal of the first transistor,

wherein a first potential is applied to a second terminal of the second transistor,

wherein a second potential which is higher than the first potential is applied to a second terminal of the third transistor,

wherein the first potential is applied to a second terminal of the fourth transistor,

wherein at least a first pulse signal is input to the first input signal generation circuit,

wherein at least a second clock signal is input to the second input signal generation circuit, and

wherein a second pulse signal is output from one of the first output terminal and the second output terminal.

2. A module comprising the shift register according to claim 1.

3. A display device comprising the shift register according to claim 1.

4. An electronic device comprising the shift register according to claim 1.

5. A shift register comprising:

a first wiring;

a second wiring;

a third wiring; and

a pulse signal output circuit electrically connected to the first, second, and third wirings, comprising;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a first circuit; and

a second circuit,

wherein a first terminal of the first transistor and a first terminal of the second transistor are electrically connected to each other to function as a first output terminal,

wherein a first terminal of the third transistor and a first terminal of the fourth transistor are electrically connected to each other to function as a second output terminal,

wherein a gate terminal of the first transistor, a gate terminal of the third transistor, and an output terminal of the first circuit are electrically connected to each other,

wherein a gate terminal of the second transistor, a gate terminal of the fourth transistor, and the second circuit are electrically connected to each other,

wherein a first clock signal is input to a second terminal of the first transistor,

wherein a first potential is applied to a second terminal of the second transistor,

wherein a second potential which is higher than the first potential is applied to a second terminal of the third transistor,

wherein the first potential is applied to a second terminal of the fourth transistor,

wherein at least a first pulse signal is input to the first circuit,

wherein at least a second clock signal is input to the second circuit, and

wherein a second pulse signal is output from one of the first output terminal and the second output terminal.

6. The shift register according to claim 5, wherein a load connected to the second output terminal is larger than a load connected to the first output terminal.

7. The shift register according to claim 5, wherein an output signal of the second circuit is input to the first circuit in addition to the first pulse signal.

8. The shift register according to claim 7,

wherein the second circuit includes a fifth transistor and a sixth transistor,

wherein a first terminal of the fifth transistor and a first terminal of the sixth transistor are electrically connected to each other to function as the output terminal of the second circuit,

wherein the second potential is applied to a second terminal of the fifth transistor,

wherein the first potential is applied to a second terminal of the sixth transistor,

wherein the first pulse signal is input to a gate terminal of the sixth transistor.

9. The shift register according to claim 7,

wherein the second circuit includes a fifth transistor, a sixth transistor, and a seventh transistor,

wherein a first terminal of the fifth transistor, a first terminal of the sixth transistor, and a first terminal of the seventh transistor are electrically connected to each other,

wherein the second potential is applied to a second terminal of the fifth transistor,

wherein the first potential is applied to a second terminal of the sixth transistor, and

wherein the first pulse signal is input to a gate terminal of the fifth transistor.

10. The shift register according to claim 5, wherein the first pulse signal and a third pulse signal are input to the second circuit in addition to the second clock signal.

11. The shift register according to claim 5,

wherein the second circuit includes an eighth transistor, and

wherein a third clock signal, the first pulse signal, and a third pulse signal are input to the second circuit in addition to the second clock signal.

12. The shift register according to claim 5, wherein a channel formation region of at least one of the first to fourth transistors includes an oxide semiconductor.

13. A module comprising the shift register according to claim 5.

14. A display device comprising the shift register according to claim 5.

15. An electronic device comprising the shift register according to claim 5.