Switching device with diode-biased field-effect transistor (FET)

• US 8,923,782 B1
• Filed: 02/20/2013
• Issued: 12/30/2014
• Est. Priority Date: 02/20/2013
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Inventors: Furino, James P. Jr., Ravindran, Arjun
• Primary Examiner(s): VO, NGUYEN THANH
• Application Number:
  US13/772,289
• Time in Patent Office: 678 Days
• Field of Search: 455/78, 455/79, 455/83, 327/365, 327/389, 327/419, 327/427, 327/434, 257/288, 257/368
• US Class Current: 455/78
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04B 1/44 Transmit/receive switching
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

Embodiments provide a switching device including a field-effect transistor (FET) having a source terminal, a drain terminal, a gate terminal, and a body terminal. The FET may be switchable between an on state, in which the FET passes a transmission signal between the source terminal and the drain terminal, and an off state, in which the FET prevents a transmission signal from passing between the source terminal and the drain terminal. The FET may receive a control signal at the gate terminal to switch the FET between the on state and the off state. The switching device may further include one or more forward diodes coupled between the gate terminal and the body terminal to bias the body terminal during the on state, and one or more reverse diodes coupled between the gate terminal and the body terminal to bias the body terminal during the off state.

Claims

1. A switching apparatus comprising:

a field-effect transistor (FET) having a gate terminal and a body terminal, the FET configured to transition between an on state and an off state, based on a control signal received at the gate terminal, to facilitate switching of a radio frequency (RF) signal;

one or more forward diodes coupled between the gate terminal and the body terminal to bias the body terminal, based on the control signal, during the on state; and

one or more reverse diodes coupled between the gate terminal and the body terminal to bias the body terminal, based on the control signal, during the off state.

2. The apparatus of claim 1, wherein the FET further includes a source terminal and a drain terminal, wherein the FET is configured to pass the RF signal from the source terminal to the drain terminal if the FET is in the on state.

3. The apparatus of claim 1, wherein the one or more forward diodes comprise one or more p-n diodes.

4. The apparatus of claim 3, wherein the one or more reverse diodes comprise one or more p-n diodes.

5. The apparatus of claim 3, wherein the one or more reverse diodes comprise one or more diode-connected n-type FETs.

6. The apparatus of claim 1, wherein the one or more forward diodes comprise one or more diode-connected p-type FETs, and wherein the one or more reverse diodes comprise one or more diode-connected n-type FETs.

7. The apparatus of claim 1, including three forward diodes and one reverse diode.

8. The apparatus of claim 1, wherein the apparatus is a silicon on insulator (SOI) device.

9. The apparatus of claim 1, wherein the one or more forward diodes are configured to bias the body terminal with a non-zero positive voltage during the on state.

10. The apparatus of claim 1, wherein the one or more reverse diodes are configured to bias the body terminal with a non-zero negative voltage during the off state.

11. The apparatus of claim 1, wherein the FET is a first FET, the forward diodes are first forward diodes, and the reverse diodes are first reverse diodes, wherein the first FET is coupled in series with an interconnect path to selectively pass the RF signal to an output terminal, and wherein the apparatus further comprises:

a second FET coupled in shunt with the interconnect path;

one or more second forward diodes coupled between a gate terminal and a body terminal of the second FET; and

one or more second reverse diodes coupled between the gate terminal and the body terminal of the second FET.

12. A circuit comprising:

a field-effect transistor (FET) having a source terminal, a drain terminal, a gate terminal, and a body terminal;

one or more forward diodes coupled in series with one another and further coupled between the gate terminal and the body terminal with a forward direction of the forward diodes oriented from the gate terminal to the body terminal; and

a reverse diode coupled between the gate terminal and the body terminal with a forward direction of the reverse diode oriented from the body terminal to the gate terminal.

13. The circuit of claim 12, wherein the one or more forward diodes comprise one or more p-n diodes.

14. The circuit of claim 13, wherein the reverse diode comprises a p-n diode.

15. The circuit of claim 13, wherein the one or more reverse diodes comprise one or more diode-connected n-type FETs.

16. The circuit of claim 12, wherein the one or more forward diodes comprise one or more diode-connected p-type FETs, and wherein the reverse diode comprises a diode-connected n-type FET.

17. The circuit of claim 12, including three to six forward diodes and one reverse diode.

18. The circuit of claim 12, wherein the FET is a silicon on insulator (SOI) device.

19. A system comprising:

a transceiver configured to provide a signal;

a power amplification module configured to receive the signal from the transceiver and amplify the signal for transmission; and

a switch module, disposed in the transceiver or in the PA module, the switch circuit having a switching device including;

a first field-effect transistor (FET) coupled in series with an interconnect path to pass the signal on the interconnect path during an on state of the switching device, the first FET including a first gate terminal and a first body terminal, wherein the first FET is responsive to a first control signal received at the first gate terminal;

a second FET coupled in shunt with the interconnect path to divert the signal from the interconnect path during an off state of the switching device, the second FET including a second gate terminal and a second body terminal, wherein the second FET is responsive to a second control signal received at the second gate terminal;

one or more forward diodes coupled between the first gate terminal and the first body terminal to bias the first body terminal, based on the first control signal, during the on state; and

one or more reverse diodes coupled between the first gate terminal and the first body terminal to bias the first body terminal, based on the first control signal, during the off state.

20. The system of claim 19, further comprising a decoder circuit coupled with the switch module to provide the first and second control signals.

21. The system of claim 19, wherein the switching device is a first switching device, wherein the switch module includes a plurality of switching devices including the first switching device, and wherein output terminals of the respective switching devices are coupled with a common output node.

22. The system of claim 21, further comprising an antenna module coupled with the output node to transmit the signal over a wireless communication network.