Double precision approximation of a single precision operation

• US 8,924,447 B2
• Filed: 10/25/2011
• Issued: 12/30/2014
• Est. Priority Date: 04/22/2011
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Babin, Dmitry N., Mazurenko, Ivan L., Parfenov, Denis V., Filippov, Alexander N., Parkhomenko, Denis V.
• Primary Examiner(s): Yaary, Michael D
• Application Number:
  US13/280,607
• Publication Number:
  US 20120271871A1
• Time in Patent Office: 1,162 Days
• Field of Search: None
• US Class Current: 708/204
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence

Abstract

A method for double precision approximation of a single precision operation is disclosed. The method may include steps (A) to (B). Step (A) may store an input value in a processor. The processor generally implements a plurality of first operations in hardware. Each first operation may receive a first variable as an argument. The first variable may be implemented in a fixed point format at a single precision. The input value may be implemented in the fixed point format at a double precision. Step (B) may generate an output value by emulating a selected one of the first operations using the input value as the argument. The emulation may utilize the selected first operation in hardware. The output value may be implemented in the fixed point format at the double precision. The emulation is generally performed by a plurality of instructions executed by the processor.

Claims

1. A method for double precision approximation of a single precision operation, comprising the steps of:

(A) storing an input value in a processor, wherein (i) said processor implements a plurality of first operations in hardware, (ii) each of said first operations receives a first variable as an argument, (iii) said first variable is implemented in a fixed point format at a single precision and (iv) said input value is implemented in said fixed point format at a double precision; and

(B) generating an output value by an emulation of a selected one of said first operations using said input value as said argument, wherein (i) said emulation utilizes said selected first operation in said hardware at said single precision, (ii) said output value is implemented in said fixed point format at said double precision and (iii) said emulation is performed by a plurality of instructions executed by said processor.

2. The method according to claim 1, wherein said emulation comprises the step of:

generating a first value as an integer representation of a most significant half of said input value.

3. The method according to claim 2, wherein said emulation further comprises the step of:

generating a second value as a difference between said input value and said first value shifted to align with said most significant half.

4. The method according to claim 3, wherein said emulation further comprises the step of:

generating a third value by performing said selected first operation in said hardware using said first value as said argument.

5. The method according to claim 4, wherein said emulation further comprises the step of:

generating a fourth value based on said first value and said second value.

6. The method according to claim 5, wherein said output value is generated by appending said fourth value to said third value.

7. The method according to claim 1, wherein said first operations emulated by said instructions comprise at least one of (i) an inverse operation, (ii) a square root operation and (iii) a square root of a difference between unity and said argument squared.

8. The method according to claim 1, wherein said emulation utilizes a plurality of second operations implemented in said hardware at said double precision.

9. The method according to claim 8, wherein said second operations comprise (i) an addition operation, (ii) a subtraction operation and (iii) a multiplication operation.

10. An apparatus comprising:

a processor configured to store an input value, wherein (i) said processor implements a plurality of first operations in hardware, (ii) each of said first operations receives a first variable as an argument, (iii) said first variable is implemented in a fixed point format at a single precision and (iv) said input value is implemented in said fixed point format at a double precision; and

a memory containing a plurality of instructions configured to generate an output value by an emulation of a selected one of said first operations using said input value as said argument, wherein (i) said emulation utilizes said selected first operation in said hardware at said single precision, (ii) said output value is implemented in said fixed point format at said double precision and (iii) said emulation is performed by said processor executing said instructions.

11. The apparatus according to claim 10, wherein said emulation generates a first value as an integer representation of a most significant half of said input value.

12. The apparatus according to claim 11, wherein said emulation generates a second value as a difference between said input value and said first value shifted to align with said most significant half.

13. The apparatus according to claim 12, wherein said emulation generates a third value by performing said selected first operation in said hardware using said first value as said argument.

14. The apparatus according to claim 13, wherein said emulation generates a fourth value based on said first value and said second value.

15. The apparatus according to claim 14, wherein said output value is generated by appending said fourth value to said third value.

16. The apparatus according to claim 10, wherein said first operations emulated by said instructions comprise at least one of (i) an inverse operation, (ii) a square root operation and (iii) a square root of a difference between unity and said argument squared.

17. The apparatus according to claim 10, wherein said emulation utilizes a plurality of second operations implemented in said hardware at said double precision.

18. The apparatus according to claim 17, wherein said second operations comprise (i) an addition operation, (ii) a subtraction operation and (iii) a multiplication operation.

19. The apparatus according to claim 10, wherein said apparatus is implemented as one or more integrated circuits.

20. An apparatus comprising:

means for processing configured to store an input value, wherein (i) said means for processing implements a plurality of first operations in hardware, (ii) each of said first operations receives a first variable as an argument, (iii) said first variable is implemented in a fixed point format at a single precision and (iv) said input value is implemented in said fixed point format at a double precision; and

means for storing a plurality of instructions configured to generate an output value by an emulation of a selected one of said first operations using said input value as said argument, wherein (i) said emulation utilizes said selected first operation in said hardware at said single precision, (ii) said output value is implemented in said fixed point format at said double precision and (iii) said emulation is performed by said means for processing executing said instructions.