Flash memory device comprising host interface for processing a multi-command descriptor block in order to exploit concurrency

• US 8,924,627 B2
• Filed: 03/28/2011
• Issued: 12/30/2014
• Est. Priority Date: 03/28/2011
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Syu, Mei-Man L., Horn, Robert L., Wilkins, Virgil V., Suryabudi, Dominic S.
• Primary Examiner(s): Rigol, Yaima
• Application Number:
  US13/073,638
• Publication Number:
  US 20120254504A1
• Time in Patent Office: 1,373 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A flash memory device is disclosed comprising a flash controller for accessing a first flash memory over a first channel and a second flash memory over a second channel. A multi-command descriptor block is received from a host, wherein the multi-command descriptor block comprises identifiers for identifying a plurality of access commands that the host is preparing to request. A first group of the access commands are selected to execute concurrently and a second group of the access commands are selected to execute concurrently. The first group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently. The second group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently.

Claims

1. A flash memory device comprising:

a plurality of flash memories, including a first flash memory and a second flash memory;

a flash controller for accessing the first flash memory over a first channel and the second flash memory over a second channel; and

a host interface operable to;

receive a multi-command descriptor block from a host, wherein the multi-command descriptor block comprises identifiers for identifying a plurality of access commands that the host is preparing to request;

select a first group of the access commands to execute concurrently and select a second group of the access commands to execute concurrently;

after receiving the multi-command descriptor block, receive the first group of access commands from the host;

execute the first group of access commands concurrently by accessing at least the first and second flash memories concurrently;

after receiving the multi-command descriptor block, receive the second group of access commands from the host; and

execute the second group of access commands concurrently by accessing at least the first and second flash memories concurrently.

2. The flash memory device as recited in claim 1, wherein:

the first group of access commands comprises a first group of write commands; and

the second group of access commands comprises a second group of write commands.

3. The flash memory device as recited in claim 2, wherein the host interface is further operable to:

receive the first group of write commands from the host including first write data; and

after receiving the first group of write commands and first write data, concurrently write the first write data to at least the first and second flash memories.

4. The flash memory device as recited in claim 3, wherein the host interface is further operable to receive the second group of write commands from the host including second write data concurrently with writing the first write data to at least the first and second flash memories.

5. The flash memory device as recited in claim 4, wherein after concurrently writing the first write data to at least the first and second flash memories, the host interface is further operable to concurrently write the second write data to at least the first and second flash memories.

6. The flash memory device as recited in claim 5, wherein after concurrently writing the second write data to at least the first and second flash memories, the host interface is further operable to notify the host of an execution status of the access commands identified by the multi-command descriptor block.

7. The flash memory device as recited in claim 1, wherein:

the first group of access commands comprises a first group of read commands; and

the second group of access commands comprises a second group of read commands.

8. The flash memory device as recited in claim 7, wherein the host interface is further operable to:

concurrently read first data from at least the first and second flash memories, wherein the first data corresponds to the first group of read commands;

receive the first group of read commands from the host; and

transfer the first data to the host.

9. The flash memory device as recited in claim 8, wherein the host interface is further operable to receive the first group of read commands from the host concurrently with reading the first data from at least the first and second flash memories.

10. The flash memory device as recited in claim 9, wherein:

after concurrently reading the first data from at least the first and second flash memories, the host interface is further operable to concurrently read second data from at least the first and second flash memories; and

the second data corresponds to the second group of read commands.

11. The flash memory device as recited in claim 1, wherein:

the first group of access commands comprises at least one write command; and

the second group of access commands comprises at least one erase command.

12. The flash memory device as recited in claim 1, wherein:

the first group of access commands comprises at least one read command; and

the second group of access commands comprises at least one erase command.

13. A method of operating a flash memory device comprising, the flash memory device comprising a plurality of flash memories, including a first flash memory and a second flash memory, and a flash controller for accessing the first flash memory over a first channel and the second flash memory over a second channel, the method comprising:

receiving a multi-command descriptor block from a host, wherein the multi-command descriptor block comprises identifiers for identifying a plurality of access commands that the host is preparing to request;

selecting a first group of the access commands to execute concurrently and selecting a second group of the access commands to execute concurrently;

after receiving the multi-command descriptor block, receiving the first group of access commands from the host;

executing the first group of access commands concurrently by accessing at least the first and second flash memories concurrently;

after receiving the multi-command descriptor block, receiving the second group of access commands from the host; and

executing the second group of access commands concurrently by accessing at least the first and second flash memories concurrently.

14. The method as recited in claim 13, wherein:

the first group of access commands comprises a first group of write commands; and

the second group of access commands comprises a second group of write commands.

15. The method as recited in claim 14, further comprising:

receiving the first group of write commands from the host including first write data; and

after receiving the first group of write commands and first write data, concurrently writing the first write data to at least the first and second flash memories.

16. The method as recited in claim 15, further comprising receiving the second group of write commands from the host including second write data concurrently with writing the first write data to at least the first and second flash memories.

17. The method as recited in claim 16, wherein after concurrently writing the first write data to at least the first and second flash memories, further comprising concurrently writing the second write data to at least the first and second flash memories.

18. The method as recited in claim 17, wherein after concurrently writing the second write data to at least the first and second flash memories, further comprising notifying the host of an execution status of the access commands identified by the multi-command descriptor block.

19. The method as recited in claim 13, wherein:

the first group of access commands comprises a first group of read commands; and

the second group of access commands comprises a second group of read commands.

20. The method as recited in claim 19, further comprising:

concurrently reading first data from at least the first and second flash memories, wherein the first data corresponds to the first group of read commands;

receiving the first group of read commands from the host; and

transferring the first data to the host.

21. The method as recited in claim 20, further comprising receiving the first group of read commands from the host concurrently with reading the first data from at least the first and second flash memories.

22. The method as recited in claim 21, wherein:

after concurrently reading the first data from at least the first and second flash memories, further comprising concurrently reading second data from at least the first and second flash memories; and

the second data corresponds to the second group of read commands.

23. The method as recited in claim 13, wherein:

the first group of access commands comprises at least one write command; and

the second group of access commands comprises at least one erase command.

24. The method as recited in claim 13, wherein:

the first group of access commands comprises at least one read command; and

the second group of access commands comprises at least one erase command.