Memory system including a controller and processors associated with memory devices

• US 8,924,661 B1
• Filed: 01/17/2010
• Issued: 12/30/2014
• Est. Priority Date: 01/18/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Shachar, Michael, Rotbard, Barak, Golov, Oren, Perlmutter, Uri, Sokolov, Dotan, Vlaiko, Julian, Schwartz, Yair
• Primary Examiner(s): Elmore, Reba I
• Application Number:
  US12/688,883
• Time in Patent Office: 1,808 Days
• Field of Search: 711/103, 711/149, 711/154, 710/40, 710/244, 712/25, 712/215, 365/45, 365/189.2, 365/239
• US Class Current: 711/158
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0628 making use of a particular technique
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.

Claims

1. A data storage system, comprising:

a host coupled to a volatile system memory;

a plurality of non-volatile memory devices arranged in one or more sets, wherein each non-volatile memory device of the plurality of non-volatile memory devices includes multiple analog memory cells arranged in groups;

a main controller configured to;

accept commands from the host;

signal the host to retrieve and send to the main controller information items stored in the volatile system memory relating to respective groups of the analog memory cells, responsive to the acceptance of the commands;

receive, from the host, the information items; and

generate recipes dependent upon the received information items, wherein each recipe includes a list of multiple memory operations to be performed sequentially in one or more of the plurality of non-volatile memory devices belonging to one of the sets; and

one or more processors, wherein each of the one or more processors is associated with a respective set of one or more of the plurality of non-volatile memory devices and is configured to;

receive one or more of the recipes from the main controller;

assign a priority to each recipe of the one or more recipes dependent upon execution times of each recipe of the one or more recipes; and

cause execution of memory operations that comprise the one or more recipes dependent upon the priority assigned to each recipe of the one or more recipes;

wherein the execution of the memory operations occurs in the one or more of the plurality of non-volatile memory devices belonging to the respective set for that processor.

2. The system according to claim 1, wherein the memory operations comprising each recipe access multiple memory pages in the plurality of non-volatile memory devices upon execution.

3. The system according to claim 1, wherein the main controller is configured to generate a recipe that instructs a given one of the one or more processors to perform at least one action selected from a group of actions comprising reading multiple pages from the plurality of non-volatile memory devices, writing multiple pages in the plurality of non-volatile memory devices, and erasing one or more memory areas in the plurality of non-volatile memory devices.

4. The system according to claim 1, wherein the main controller is configured to generate a recipe that instructs a given one of the one or more processors to copy multiple pages from one or more first locations in the plurality of non-volatile memory devices to a second location in the plurality of non-volatile memory devices.

5. The system according to claim 4, wherein the recipe instructs the given one of the one or more processors to modify at least one of the pages read from the first locations and to write the modified pages to the second location.

6. The system according to claim 1, wherein the main controller is configured to generate a recipe that instructs a given one of the one or more processors to:

read first data from a first location in the plurality of non-volatile memory devices;

use the first data as an address pointing to a second location in the plurality of non-volatile memory devices; and

read second data from the second location using the address.

7. The system according to claim 1, wherein each of the one or more processors is configured to send to the main controller a request for exchanging data between that processor and the main controller, and wherein the main controller is configured to exchange the data with that processor responsively to the request.

8. The system according to claim 1, wherein the commands accepted from the host specify logical addresses, and wherein the main controller is configured to translate the logical addresses into respective physical storage locations in the plurality of non-volatile memory devices and is configured to specify the physical storage locations in the recipes.

9. The system according to claim 8, wherein each one of the one or more processors is configured to:

store in the plurality of non-volatile memory devices given data and a logical address corresponding to the given data;

receive a recipe instructing that processor to retrieve the given data from the plurality of non-volatile memory devices, wherein the recipe indicates the logical address;

read the given data and the logical address from the plurality non-volatile memory devices; and

detect an error condition corresponding to a mismatch between the logical address indicated in the recipe and the logical address read from the plurality of non-volatile memory devices.

10. The system according to claim 1, wherein the main controller is configured to assign respective priorities to the recipes, and wherein each of the one or more processors is configured to execute the recipes in accordance with the priorities.

11. The system according to claim 1, wherein each of the one or more processors is configured to receive two or more of the recipes in a first order, and is configured to execute the recipes in a second order different from the first order.

12. The system according to claim 1, wherein each of the one or more processors is configured to:

identify that a first recipe comprises a first write operation addressed to a given location in the plurality of non-volatile memory devices;

identify that a second recipe comprises a second write operation that is subsequent to the first write operation, wherein the second write operation is addressed to-the given location in the plurality of non-volatile memory devices; and

inhibit execution of the first write operation.

13. The system according to claim 1, wherein each of the one or more processors is configured to:

identify that a first recipe comprises a first read operation addressed to a given location in the plurality of non-volatile memory devices;

identify that a second recipe comprises a second read operation that is subsequent to the first read operation, wherein the read operation comprises an address to the given location in the plurality of non-volatile memory devices; and

inhibit execution of the second read operation.

14. The system according to claim 1, wherein each of the one or more processors is configured to:

identify that a first recipe comprises a write operation that writes a value to a given location in the plurality of non-volatile memory devices;

identify that a second recipe comprises a read operation that is addressed to the given location and is subsequent to the first write operation; and

execute the read operation using an internally-buffered version of the value obtained from the write operation, without applying the read operation to the plurality of non-volatile memory devices.

15. The system according to claim 1, wherein the one or more processors are configured to extract the information items from the recipe addressing a given group and cause execution, in the plurality of non-volatile memory devices, of memory operations specified in the recipe responsive to the extracted value.

16. The system according to claim 1, wherein the information items comprises at least one property type selected from a group of types comprising:

Programming and Verification (PV) levels used in programming the memory cells, read thresholds used in reading the memory cells, endurance measures of the memory cells, elapsed times since latest programming of the memory cells, estimates of read disturb in the memory cells, and time-temperature integral values computed over the memory cells.

17. The system according to claim 1, wherein the main controller is configured to convert a given host command to a set of one or more recipes and send a command completion indication to the host after sending the set of the recipes to the one or more processors, irrespective of execution of the recipes in the set.

18. The system according to claim 1, further comprising a volatile memory coupled to the main controller, wherein the main controller is configured to:

store in the volatile memory a linked list of data items representing data, each data item comprising a portion of the data and a pointer to a next data item on the list; and

generate a recipe that instructs a given one of the one or more processors to store the data in the plurality of non-volatile memory devices and points to a first data item on the linked list of data items.

19. A method for data storage, comprising:

accepting commands from a host at a main controller, wherein the commands relate to data storage in a plurality of non-volatile memory devices arranged in one or more sets;

wherein the plurality of non-volatile memory devices include multiple analog memory cells arranged in groups;

signaling, by the main controller, to the host to retrieve information items relating to the groups of analog memory cells from a volatile system memory and send the information items to the main controller;

receiving, by the main controller, the information items;

converting, by the main controller, the commands into recipes dependent upon the received information items, wherein each recipe includes a list of multiple memory operations to be performed sequentially in one or more of the plurality of non-volatile memory devices belonging to one of the sets;

receiving, by at least one processor of one or more processors, the one or more recipes

wherein each of the one or more processors is associated with a respective set of the plurality of non-volatile memory devices;

assigning, by the at least one processor of the one or more processors, a priority to each recipe of the one or more recipes dependent upon a respective execution time of each recipe of the one or more recipes;

executing, by the at least one processor of the one or more processors, memory operations specified in the one or more of the recipes in the plurality of non-volatile memory devices belonging to the respective set for the at least one processor dependent upon the priority assigned to each recipe of the one or more recipes.

20. The method according to claim 19, wherein the memory operations specified in each recipe access multiple memory pages in the plurality of non-volatile memory devices upon execution.

21. The method according to claim 19, wherein converting the commands into the recipes comprises generating a recipe that instructs a given one of the one or more processors to perform at least one action selected from a group of actions comprising:

reading multiple pages from the plurality of non-volatile memory devices, writing multiple pages in the plurality of non-volatile memory devices, and erasing one or more memory areas in the plurality of non-volatile memory devices.

22. The method according to claim 19, wherein converting the commands into the recipes comprises generating a recipe that instructs a given one of the one or more processors to copy multiple pages from one or more first locations in the plurality of non-volatile memory devices to a second location in the plurality of non-volatile memory devices.

23. The method according to claim 22, wherein the recipe instructs the given one of the one or more processors to modify at least one of the pages read from the first locations and to write the modified pages to the second location.

24. The method according to claim 19, wherein converting the commands into the recipes comprises generating a recipe that instructs a given one of the one or more processors to:

read first data from a first location in the plurality of non-volatile memory devices;

use the first data as an address pointing to a second location in the plurality of non-volatile memory devices; and

read second data from the second location using the address.

25. The method according to claim 19, wherein the commands accepted from the host specify logical addresses, and wherein converting the commands into the recipes comprises translating the logical addresses into respective physical storage locations in the plurality of non-volatile memory devices.

26. The method according to claim 25, wherein executing the one or more of the recipes comprises:

storing in the plurality of non-volatile memory devices given data and a logical address corresponding to the given data;

in association with copying the given data to an alternative physical storage location in the plurality of non-volatile memory devices, reading the logical address of the given data from the plurality of non-volatile memory devices and determining that the read logical address is associated with the alternative physical storage location.

27. The method according to claim 19, wherein converting the commands into the recipes comprises assigning respective priorities to the recipes and wherein executing the one or more of the recipes comprises executing the one or more of the recipes in accordance with their respective priorities.

28. The method according to claim 19, wherein executing the one or more of the recipes comprises receiving two or more of the recipes in a first order and executing the recipes in a second order, different from the first order.

29. The method according to claim 19, wherein executing the one or more of the recipes comprises:

identifying that a first recipe comprises a first write operation addressed to a given location in the plurality of non-volatile memory devices;

identifying that a second recipe comprises a second write operation that is subsequent to the first write operation, wherein the second write operation comprises an address of the given location in the plurality of non-volatile memory devices; and

inhibiting execution of the first write operation.

30. The method according to claim 19, wherein executing the one or more of the recipes comprises:

identifying that a first recipe comprises a first read operation addressed to a given location in the plurality of non-volatile memory devices;

identifying that a second recipe comprises a second read operation that is subsequent to the first read operation, wherein the second read operation comprises an address of the given location in the plurality of non-volatile memory devices; and

inhibiting execution of the second read operation.

31. The method according to claim 19, wherein the information items comprise at least one of:

Programming and Verification (PV) levels used in programming the memory cells, read thresholds used in reading the memory cells, endurance measures of the memory cells, elapsed times since latest programming of the memory cells, estimates of read disturb in the memory cells, and time-temperature integral values computed over the memory cells.

32. The method according to claim 19, further comprising storing one or more read threshold values applicable to each of one or more of the groups and updating the one or more read threshold values.

33. The method according to claim 19, wherein converting the commands into the recipes comprises converting a given host command to a set of one or more recipes and sending a command completion indication to the host after sending the set of the one or more recipes to the one or more processors, irrespective of execution of the recipes in the set.

34. The method according to claim 19, wherein converting the commands into the recipes comprises storing in volatile memory a linked list of data items representing data, each data item comprising a portion of the data and a pointer to a next data item on the list, and generating a recipe that instructs a given one of the one or more processors to store the data in the plurality of non-volatile memory devices and points to a first data item on the linked list of data items.