Data security and access tracking in memory

• US 8,925,098 B2
• Filed: 01/10/2013
• Issued: 12/30/2014
• Est. Priority Date: 11/15/2012
• Status: Expired due to Fees

• Current Assignee: Elwha LLC (Intellectual Ventures LLC)
• Original Assignee: Elwha LLC (Intellectual Ventures LLC)
• Inventors: Hyde, Roderick A., Pasch, Nicholas F., Tegreene, Clarence T.
• Primary Examiner(s): Song, Hosuk
• Application Number:
  US13/738,747
• Publication Number:
  US 20140137271A1
• Time in Patent Office: 719 Days
• Field of Search: 713/172, 713/174, 713189-194, 726 26- 30, 711100-105, 711/111
• US Class Current: 726/26
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 21/00 Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2221/2101 Auditing as a secondary aspect
• CPC Class Codes: G06F 2221/2141 Access rights, e.g. capability lists, access control lists, access tables, access matrices
• CPC Class Codes: G06F 2221/2143 Clearing memory, e.g. to prevent the data from being stolen
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory device includes but is not limited to a substrate, a non-volatile memory array integrated on the substrate, and data security logic integrated with the non-volatile memory array on the substrate. The data security logic is operable to perform at least one data security function associated with the non-volatile memory array.

Claims

1. A memory device comprising:

a substrate;

a non-volatile memory array integrated on the substrate; and

data security logic integrated with the non-volatile memory array on the substrate, the data security logic operable to perform at least one data security function associated with the non-volatile memory array, wherein;

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes read-once logic operable to read data from a selected portion of the non-volatile memory array for usage, flag the selected portion of the non-volatile memory array, and throw an exception for subsequent reads of the flagged selected portion of the non-volatile memory array.

2. The memory device according to claim 1 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes read-once logic operable to enforce a read-once restriction on a selected portion of the non-volatile memory array.

3. The memory device according to claim 1 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes read-once logic operable to read data from a selected portion of the non-volatile memory array for usage, and destroy the data in the selected portion of the non-volatile memory array.

4. The memory device according to claim 1 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes read-once logic operable to read data from a selected portion of the non-volatile memory array for usage, destroy the data in the selected portion of the non-volatile memory array, and throw an exception for subsequent reads of the selected portion of the non-volatile memory array.

5. The memory device according to claim 1 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes read-once logic operable to receive a request to read a selected portion of the non-volatile memory array, and respond to the request to read a selected portion of the non-volatile memory array including determining whether data in the selected portion of the non-volatile memory array was previously read, determining whether the previously read data in the selected portion of the non-volatile memory array was deleted, and reading data from the selected portion of the non-volatile memory array only if the previously read data was deleted.

6. The memory device according to claim 1 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes counting logic operable to count a number of times data is read from a selected portion of the non-volatile memory array.

7. The memory device according to claim 1 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes counting logic operable to count a number of times data is read from a selected portion of the non-volatile memory array and a number of times the data is written to the selected portion of the non-volatile memory array.

8. A memory device comprising:

a substrate;

a non-volatile memory array integrated on the substrate; and

data security logic integrated with the non-volatile memory array on the substrate, the data security logic operable to perform at least one data security function associated with the non-volatile memory array, wherein;

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes counting logic operable to count a number of times data is read from a selected portion of the non-volatile memory array and a number of times the data is written to the selected portion of the non-volatile memory array, and throw an exception based on the counts.

9. The memory device according to claim 8 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes read-once logic operable to read data from a selected portion of the non-volatile memory array for usage, and flag the selected portion of the non-volatile memory array.

10. The memory device according to claim 8 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes counting logic operable to count a number of times data is read from a selected portion of the non-volatile memory array, and throw an exception for a count greater than one of the number of times data is read from the selected portion of the non-volatile memory array.

11. The memory device according to claim 8 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes counting logic operable to count a number of times data is read from a selected portion of the non-volatile memory array and a number of times the data is written to the selected portion of the non-volatile memory array, and control access to the selected portion of the non-volatile memory array based on the counts.

12. The memory device according to claim 8 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes counting logic and process identification logic operable in combination to manage a number of accesses of a selected portion of the non-volatile memory array and by what processes.

13. The memory device according to claim 8 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes counting logic and process identification logic operable in combination to manage a number of accesses of a selected portion of the non-volatile memory array and by what processes and at what times.

14. A memory device comprising:

a substrate;

a non-volatile memory array integrated on the substrate; and

data security logic integrated with the non-volatile memory array on the substrate, the data security logic operable to perform at least one data security function associated with the non-volatile memory array, wherein;

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes process identification logic operable to identify a process and determine whether the process is enabled to read data from a selected portion of the non-volatile memory array and to throw an exception if the process is not enabled to read the data from the selected portion of the non-volatile memory array.

15. The memory device according to claim 14 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes process identification logic operable to identify a process and determine whether the process is enabled to read data from a selected portion of the non-volatile memory array and allow the enabled process to read the data from the selected portion of the non-volatile memory array.

16. The memory device according to claim 14 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes process identification logic operable to identify a process and determine whether the process is identified as enabled to read data from a selected portion of the non-volatile memory array and to throw an exception if the process is not identified as enabled to read the data from the selected portion of the non-volatile memory array.

17. The memory device according to claim 14 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes process identification logic operable to identify a plurality of processes and determine whether the plurality of processes is enabled to communicate using a selected portion of the non-volatile memory array and to access the selected portion of the non-volatile memory array if enabled to communicate.

18. The memory device according to claim 14 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes process identification logic operable to identify a plurality of processes and determine whether the plurality of processes is enabled to communicate using a selected portion of the non-volatile memory array and to disallow access to the selected portion of the non-volatile memory array if not enabled to communicate.

19. The memory device according to claim 14 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes process identification logic operable to identify a plurality of processes and determine whether the plurality of processes is enabled to communicate using a selected portion of the non-volatile memory array and to throw an exception if not enabled to communicate.

20. The memory device according to claim 14 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes counting logic and process identification logic operable in combination to manage access to a selected portion of the non-volatile memory array.

21. A memory device comprising:

a substrate;

a non-volatile memory array integrated on the substrate;

data security logic integrated with the non-volatile memory array on the substrate, the data security logic operable to perform at least one data security function associated with the non-volatile memory array; and

a protection key register integrated with the data security logic and the non-volatile memory array on the substrate, wherein;

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes protection key logic operable to manage access to a selected portion of the non-volatile memory array based on information in the protection key register.

22. The memory device according to claim 21 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes protection key logic operable to receive information and write the received information to the protection key register.

23. The memory device according to claim 21 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes protection key logic operable to read data from a selected portion of the non-volatile memory array only if authorized by information in the protection key register.

24. The memory device according to claim 21 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes protection key logic operable to write data to a selected portion of the non-volatile memory array only if authorized by information in the protection key register.

25. A memory device comprising:

a substrate;

a non-volatile memory array integrated on the substrate; and

data security logic integrated with the non-volatile memory array on the substrate, the data security logic operable to perform at least one data security function associated with the non-volatile memory array, wherein;

the non-volatile memory array further includes a plurality of non-volatile memory segments characterized by a respective plurality of non-volatile memory types; and

the data security logic operable to perform at least one data security function associated with the non-volatile memory array is operable to perform at least one data security function for the non-volatile memory segments selectively based on one or more of the plurality of non-volatile memory types.

26. The memory device according to claim 25 further comprising:

at least one sensor operable to detect at least one operating condition, wherein;

the data security logic operable to perform at least one data security function associated with the non-volatile memory array is operable to perform at least one data security function for the non-volatile memory array selectively based on the at least one operating condition.

27. The memory device according to claim 25 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array is operable to access a time signal and perform at least one data security function for the non-volatile memory array based on the time signal.

28. The memory device according to claim 25 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array is operable to monitor phenomena detectable at the memory device and perform at least one data security function for the non-volatile memory array based on the monitored phenomena.

29. The memory device according to claim 25 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array is operable to accumulate and communicate information about phenomena associated with at least one entity in association with the memory device and perform at least one data security function for the non-volatile memory array based on the monitored phenomena.

30. The memory device according to claim 25 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes encryption logic operable to perform at least one encryption/decryption function associated with the non-volatile memory array and operable to read data from a selected portion of the non-volatile memory array only if authorized by results of the encryption/decryption function.

31. The memory device according to claim 25 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes encryption logic operable to perform at least one encryption/decryption function associated with the non-volatile memory array that holds at least one encryption key secure from a device external to the memory device and operable to read data from a selected portion of the non-volatile memory array only if enabled by the encryption key.

32. The memory device according to claim 25 wherein:

the data security logic operable to perform at least one data security function associated with the non-volatile memory array further includes hash logic operable to perform a hash function associated with the non-volatile memory array and operable to read data from a selected portion of the non-volatile memory array only if authorized by results of the hash function.