Method of forming bus line designs for large-area OLED lighting

• US 8,927,308 B2
• Filed: 05/12/2011
• Issued: 01/06/2015
• Est. Priority Date: 05/12/2011
• Status: Active Grant

• Current Assignee: Universal Display Corporation
• Original Assignee: Universal Display Corporation
• Inventors: Pang, Huiqing, Levermore, Peter, Krall, Emory, Rajan, Kamala, Ma, Ruiqing (Ray), Burrows, Paul E.
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): Dulka, John P
• Application Number:
  US13/106,733
• Publication Number:
  US 20120286298A1
• Time in Patent Office: 1,335 Days
• Field of Search: 257/88, 257/E33.062, 257/E33.066, 313/505, 438/34, 438/99
• US Class Current: 438/34
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10K 50/11 characterised by the electroluminescent [EL] layers
• CPC Class Codes: H10K 50/805 Electrodes
• CPC Class Codes: H10K 50/81 Anodes
• CPC Class Codes: H10K 50/814 combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
• CPC Class Codes: H10K 50/82 Cathodes
• CPC Class Codes: H10K 50/824 combined with auxiliary electrodes
• CPC Class Codes: H10K 59/84 Parallel electrical configurations of multiple OLEDs
• CPC Class Codes: H10K 59/86 Series electrical configurations of multiple OLEDs
• CPC Class Codes: H10K 85/211 Fullerenes, e.g. C60
• CPC Class Codes: H10K 85/322 comprising boron
• CPC Class Codes: H10K 85/381 Metal complexes comprising a group IIB metal element, e.g. comprising cadmium, mercury or zinc
• CPC Class Codes: H10K 85/626 containing more than one polycyclic condensed aromatic rings, e.g. bis-anthracene
• CPC Class Codes: H10K 85/654 comprising only nitrogen as heteroatom H10K85/652 takes precedence
• CPC Class Codes: H10K 85/655 comprising only sulfur as heteroatom
• CPC Class Codes: H10K 85/6565 Oxadiazole compounds
• CPC Class Codes: H10K 85/6572 : comprising only nitrogen in the heteroaromatic polycondensed ring system, e.g. phenanthroline or carbazole

Abstract

Systems, and methods for the design and fabrication of OLEDs, including large-area OLEDs with metal bus lines, are provided. For a given panel area dimension, target luminous emittance, OLED device structure and efficiency (as given by the JVL characteristics of an equivalent small area pixel), and electrical resistivity and thickness of the bus line material and electrode onto which the bus lines are disposed, a bus line pattern may be designed such that Fill Factor (FF), Luminance Uniformity (U) and Power Loss (PL) may be optimized. One general design objective may be to maximize FF, maximize U and minimize PL. Another approach may be, for example, to define minimum criteria for U and a maximum criteria for PL, and then to optimize the bus line layout to maximize FF. OLED panels including bus lines with different resistances (R1) along a length of the bus line are also described.

Claims

1. A method of manufacturing a light emitting panel with a plurality of active areas and a plurality of bus lines, the method comprising:

determining equipotential lines in the absence of bus lines, on at least one electrode between at least one pair of electrode contacts with the same electrical polarity;

determining an arrangement for a plurality of bus lines between the at least one pair of electrode contacts, the plurality of bus lines arranged to run perpendicular to the determined equipotential lines; and

forming the plurality of bus lines in electrical contact with the at least one electrode according to the determined arrangement.

2. The method of claim 1, wherein the at least one pair of electrode contacts includes a pair of anode contacts, the at least one electrode is an anode, and the plurality of bus lines are arranged between the pair of anode contacts.

3. The method of claim 1, wherein the at least one pair of electrode contacts includes a pair of cathode contacts, the at least one electrode is a cathode, and the plurality of bus lines are arranged between the pair of cathode contacts.

4. The method of claim 1, wherein:

a panel area is rectangular;

the at least one pair of electrode contacts includes contacts of the same polarity on each side of the panel area;

the plurality of bus lines are arranged such that a first set of the bus lines closely run perpendicular to one pair of opposing sides of the panel area, and a second set of the bus lines closely run perpendicular to the other pair of opposing sides of the panel area; and

the first set of the bus lines and the second set of the bus lines are in electrical contact with the at least one electrode.

5. The method of claim 1, wherein:

a panel area is rectangular;

a first pair of opposing sides of the panel area have a relatively long length compared to a second pair of opposing sides of the panel area;

the at least one pair of electrode contacts includes contacts of the same polarity on at least the first pair of opposing sides of the panel area; and

the plurality of bus lines are arranged to closely run only perpendicular to the first pair of opposing sides of the panel area.

6. The method of claim 1, wherein:

a panel area includes a plurality of rectangular active areas;

first pairs of opposing sides of the active areas have a relatively long length compared to second pairs of opposing sides of the active areas; and

the active areas are arranged such that the first pair of opposing sides of the active areas closely run parallel to the plurality of bus lines.

7. The method of claim 1, wherein:

a panel area comprises a circular shape;

the equipotential lines are concentric; and

the bus lines are arranged to run along radii extending from an edge of the circular shape to a center of the circular shape.

8. The method of claim 1, wherein a footprint of the outer dimensions of the at least one pair of electrode contacts is equal to or larger than a perimeter footprint of a panel area.

9. The method of claim 1, wherein:

the at least one electrode includes a first electrode and a second electrode;

equipotential lines are determined for the first electrode and the second electrode;

the at least one pair of electrode contacts includes a first set of electrode contacts for the first electrode and a second set of electrode contacts for the second electrode;

wherein the first electrode is between the first set of electrode contacts and the second electrode is between the second set of electrode contacts;

a first set of the plurality of bus lines are arranged between the first set of electrode contacts and a second set of the plurality of bus lines are arranged between the second set of electrode contacts; and

the first set of bus lines are formed in electrical contact with the first electrode and the second set of bus lines are formed in electrical contact with the second electrode.

10. The method of claim 9, wherein the first electrode is anode and the second electrode is cathode.

11. The method of claim 1, wherein:

a panel area is rectangular;

the at least one pair of electrode contacts includes a first set of electrode contacts of the same electrical polarity on opposite sides of the panel area; and

the plurality of bus lines are arranged in electrical contact with the at least one electrode to closely run perpendicular to the first set of electrode contacts.

12. The method of claim 11, wherein:

the at least one electrode includes a first electrode and a second electrode, the second electrode separate, and opposite electrical polarity, from the first electrode;

the equipotential lines are determined for the first electrode and the second electrode;

the at least one pair of electrode contacts includes the first set of electrode contacts, for the first electrode, and a second set of electrode contacts, for the second electrode;

a first set of the plurality of bus lines are arranged between the first set of electrode contacts;

a second set of the plurality of bus lines are arranged between the second set of electrode contacts;

the first set of bus lines are formed in electrical contact with the first electrode and perpendicular to the first set of electrode contacts; and

the second set of bus lines are formed in electrical contact with the second electrode and perpendicular to the second set of electrode contacts.

13. The method of claim 11, wherein the first set of electrode contacts are anode contacts.

14. The method of claim 11, wherein the first set of electrode contacts are cathode contacts.

15. The method of claim 1, further comprising calculating a minimum bus line width for the plurality bus lines based on a given working condition,

wherein the plurality of bus lines are formed according to the calculated minimum bus line width.

16. The method of claim 15, wherein the working condition includes a target luminous emittance, and one or the combination of two of a minimum Uniformity, a minimum Fill Factor and a maximum Power Loss.

17. The method of claim 16, wherein the calculating the minimum bus line width further comprises:

providing device current density-voltage-luminance (JVL) data of an equivalent small area pixel;

providing horizontal dimensions of the panel area;

providing resistivity values and thickness of bus line material and the electrode onto which the bus line is disposed; and

optimizing values for at least one of a maximum Fill Factor (FF), a maximum luminance uniformity (U) and a minimum power loss (PL) for the target working condition.

18. A method of manufacturing a light emitting panel, wherein the panel area comprises a plurality of active areas and a plurality of bus lines, the method comprising:

providing horizontal dimensions of the panel area;

providing device current density-voltage-luminance (JVL) data of an equivalent small area pixel;

providing resistivity values and thickness of bus line material and an electrode onto which the bus line is disposed;

providing a target working condition for the light emitting panel;

calculating at least one width of metal bus lines based on the horizontal dimensions of the panel area, device JVL data, resistivity and thickness of bus line material and the electrode onto which the bus line is disposed, and the target working condition; and

forming the plurality of bus lines according to the at least one calculated value.

19. The method of claim 18, wherein the working condition includes a target luminous emittance and one or the combination of two of a minimum uniformity, a minimum Fill Factor and a maximum power loss.

20. The method of claim 18, wherein the calculating at least one width of metal bus lines comprises solving for a Fill Factor (FF)>

70% and a Luminance Uniformity (U)>

80%.

21. The method of claim 18, wherein the light emitting panel has a panel area >

50 cm² and the calculating at least one width of metal bus lines comprises solving for a Fill Factor (FF)>

80% and a Luminance Uniformity (U)>

90%.

22. The method of claim 18, wherein the light emitting panel has a panel area >

50 cm² and the calculating at least one width of metal bus lines comprises solving for a Fill Factor (FF)>

90% and a Luminance Uniformity (U)>

90%.

23. The method of claim 18, wherein the panel area is rectangular shaped with length X and width Y, the method further comprising solving for Fill Factor (FF) according to the equation:

24. The method of claim 18, wherein, with a bus line running along a y direction, each segment has a current I(y), resistivity p(y), thickness t(y), and width W_x(y), and an angle θ

(y) with respect to y, and the calculating the at least one width of metal bus lines comprises calculating the width along an x direction (W_x) and solving for a potential drop (Δ

V) along the bus line of length L according to the equation;

25. The method of claim 18, wherein the bus lines are formed to run substantially perpendicular to the equipotential lines.

26. The method of claim 18, wherein:

the panel area is rectangular and includes at least one pair of electrode contacts of the same polarity on each side of the panel area;

the plurality of bus lines are arranged such that a first set of the bus lines closely run perpendicular to one pair of opposing sides of the panel area, and a second set of the bus lines closely run perpendicular to the other pair of opposing sides of the panel area; and

the first set of the bus lines and the second set of the bus lines are in electrical contact with the at least one electrode.

27. The method of claim 18, wherein:

the panel area is rectangular and includes at least one pair of electrode contacts of the same polarity;

a first pair of opposing sides of the panel area have a relatively long length compared to a second pair of opposing sides of the panel area;

the at least one pair of electrode contacts includes contacts of the same polarity on at least the first pair of opposing sides of the panel area; and

the plurality of bus lines are arranged to closely run only perpendicular to the first pair of opposing sides of the panel area.

28. The method of claim 18, wherein:

the panel area includes a plurality of rectangular active areas;

first pairs of opposing sides of the active areas have a relatively long length compared to second pairs of opposing sides of the active areas; and

the active areas are arranged such that the first pair of opposing sides of the active areas closely run parallel to the plurality of bus lines.

29. The method of claim 18, wherein the panel area operates at luminous emittance greater than 8,000 lm/m² inclusive of light extraction enhancement.

30. The method of claim 18, wherein a footprint of outer dimensions of at least one pair of electrode contacts connected to the bus lines is equal to or larger than a perimeter footprint of the panel area.

31. The method of claim 18, wherein the calculating at least one width of metal bus lines includes providing a length of at least one active area (S) and a height of this one active area (H).

32. The method of claim 31, wherein the calculating at least one width of metal bus lines includes calculating at least one of a width of metal bus lines along an x direction (W_x) and width of metal bus lines along a y direction (W_y), based on S, H, horizontal dimensions of the panel area, device JVL data, resistivity and thickness of bus line material and the electrode onto which the bus line is disposed, and the target working condition.