MEMS device having variable gap width and method of manufacture

• US 8,927,311 B2
• Filed: 02/16/2011
• Issued: 01/06/2015
• Est. Priority Date: 02/16/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: McNeil, Andrew C., Lin, Yizhen, Zhang, Lisa Z.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Parker, John M
• Application Number:
  US13/028,930
• Publication Number:
  US 20120204642A1
• Time in Patent Office: 1,420 Days
• Field of Search: 438/51, 438/52, 438/121, 438/125
• US Class Current: 438/52
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2203/058 Rotation out of a plane parallel to the substrate
• CPC Class Codes: B81B 2203/06 Devices comprising elements which are movable in relation to each other, e.g. slidable or rotatable
• CPC Class Codes: B81B 3/0008 Structures for avoiding electrostatic attraction, e.g. avoiding charge accumulation
• CPC Class Codes: B81B 3/0056 Adjusting the distance between two elements, at least one of them being movable, e.g. air-gap tuning
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 2015/0831 the mass being of the paddle type having the pivot axis between the longitudinal ends of the mass, e.g. see-saw configuration
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: Y10T 29/49156 with selective destruction of conductive paths

Abstract

A MEMS device (40) includes a base structure (42) and a microstructure (44) suspended above the structure (42). The base structure (42) includes an oxide layer (50) formed on a substrate (48), a structural layer (54) formed on the oxide layer (50), and an insulating layer (56) formed over the structural layer (54). A sacrificial layer (112) is formed overlying the base structure (42), and the microstructure (44) is formed in another structural layer (116) over the sacrificial layer (112). Methodology (90) entails removing the sacrificial layer (112) and a portion of the oxide layer (50) to release the microstructure (44) and to expose a top surface (52) of the substrate (48). Following removal, a width (86) of a gap (80) produced between the microstructure (44) and the top surface (52) is greater than a width (88) of a gap (84) produced between the microstructure (44) and the structural layer (54).

Claims

1. A method for producing a microelectromechanical systems (MEMS) device comprising:

providing a substrate;

forming a first dielectric layer overlying said substrate;

forming a first structural layer overlying said first dielectric layer, wherein said forming said first structural layer comprises producing a sense plate in said first structural layer;

forming a second dielectric layer over said first structural layer to produce a base structure in which a portion of said first dielectric layer is exposed from both of said first structural layer and said second dielectric layer, wherein said sense plate is laterally displaced away from said portion of said first dielectric layer in said base structure, and said sense plate includes openings extending through said sense plate to expose a second portion of said first dielectric layer;

forming a sacrificial layer overlying said portion of said first dielectric layer and said second dielectric layer of said base structure;

forming a second structural layer overlying said sacrificial layer, wherein said forming said second structural layer comprises forming a proof mass in said second structural layer; and

selectively removing said sacrificial layer and said portion of said first dielectric layer to expose a top surface of said substrate underlying said portion of said first dielectric layer and to release said proof mass such that said proof mass is movable relative to said base structure, wherein said selectively removing operation further comprises removing said second portion of said first dielectric layer underlying said sense plate via said openings.

2. A method as claimed in claim 1 wherein said selectively removing operation comprises producing a first gap between said proof mass and said top surface of said substrate and a second gap between said proof mass and said first structural layer, a first width of said first gap being greater than a second width of said second gap.

3. A method as claimed in claim 2 wherein said top surface of said substrate underlying said microstructure defines a non-sensing region for said MEMS device.

4. A method as claimed in claim 1 wherein said first dielectric layer is an oxide layer and said second dielectric layer is a nitride layer.

5. A method as claimed in claim 1 wherein said substrate is a silicon substrate, and said selectively removing operation exposes said top surface of said silicon substrate underlying said portion of said first dielectric layer.

6. A method for producing a microelectromechanical systems (MEMS) device comprising:

providing a substrate;

forming a first dielectric layer overlying said substrate;

forming a first structural layer overlying said first dielectric layer, wherein said forming said first structural layer comprises patterning said first structural layer to form at least one sense plate having openings extending through said at least one sense plate;

forming a second dielectric layer over said first structural layer to produce a base structure in which a portion of said first dielectric layer is exposed from both of said first structural layer and said second dielectric layer;

forming a sacrificial layer overlying said portion of said first dielectric layer and said second dielectric layer of said base structure;

forming a second structural layer overlying said sacrificial layer, wherein said forming said second structural layer comprises forming a proof mass in said second structural layer; and

selectively removing said sacrificial layer and said portion of said first dielectric layer to expose a top surface of said substrate underlying said portion of said first dielectric layer and to release said proof mass such that said proof masss is movable relative to said base structure, wherein said selectively removing operation comprises etching said portion of said first dielectric layer via said openings.

7. A method as claimed in claim 6 wherein said forming said second dielectric layer comprises patterning said second dielectric layer such that said at least one sense plate having said openings is exposed from said second dielectric layer.

8. A method as claimed in claim 6 wherein said etching operation comprises undercutting said at least one sense plate to partially remove said first dielectric layer underlying said at least one sense plate.

9. A method for producing a microelectromechanical systems (MEMS) device comprising:

forming a first dielectric layer overlying a substrate;

forming a first structural layer overlying said first dielectric layer, wherein a sense plate is produced in said first structural layer and said forming said first structural layer comprises forming openings extending through said sense plate;

forming a second dielectric layer over said first structural layer to produce a base structure in which a portion of said first dielectric layer is exposed from both of said first structural layer and said second dielectric layer, and said sense plate is laterally displaced away from said portion of said first dielectric layer in said base structure;

forming a sacrificial layer overlying said portion of said first dielectric layer and said second dielectric layer of said base structure;

forming a second structural layer overlying said sacrificial layer, said forming said second structural layer including forming a proof mass in said second structural layer; and

selectively removing said sacrificial layer and said portion of said first dielectric layer to expose a top surface of said substrate underlying said portion of said first dielectric layer, said selectively removing operation further removing said sacrificial layer underlying said second structural layer to expose said sense plate and to release said proof mass such that said proof mass is spaced apart from said base structure and said proof mass is movable relative to said base structure, and said selectively removing operation comprising etching a second portion of said first dielectric layer underlying said sense plate via said openings, wherein a first gap is produced between said proof mass and said top surface of said substrate and a second gap is produced between said proof mass and said sense plate, a first width of said first gap being greater than a second width of said second gap.

10. A method as claimed in claim 9 wherein said top surface of said substrate underlying said microstructure defines a non-sensing region for said MEMS device.

11. A method as claimed in claim 9 wherein said etching operation comprises undercutting said at least one sense plate to partially remove said first dielectric layer underlying said at least one sense plate.

12. A method as claimed in claim 9 wherein said forming said second dielectric layer comprises patterning said second dielectric layer such that said sense plate is exposed from said second dielectric layer.

13. A method as claimed in claim 9 wherein said first dielectric layer is an oxide layer and said second dielectric layer is a nitride layer.

14. A method as claimed in claim 9 wherein said substrate is a silicon substrate, and said selectively removing operation exposes said top surface of said silicon substrate underlying said portion of said first dielectric layer.