High threshold voltage NMOS transistors for low power IC technology

• US 8,927,361 B2
• Filed: 03/13/2013
• Issued: 01/06/2015
• Est. Priority Date: 03/20/2009
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Booth, Roger Allen Jr., Chan, Victor W. C., Kanike, Narasimhulu, Shang, Huiling, Vidya, Varadarajan, Yuan, Jun
• Primary Examiner(s): Gurley, Lynne
• Assistant Examiner(s): Webb, Vernon P
• Application Number:
  US13/798,573
• Publication Number:
  US 20130196476A1
• Time in Patent Office: 664 Days
• Field of Search: 257/E21.633, 257/369, 257/E27.062, 438/217, 438/199, 438/286
• US Class Current: 438/217
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Abstract

Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

Claims

1. A method of making a semiconductor device having transistors of a first conductivity type but exhibiting different electrical characteristics, said method comprising steps of

forming a plurality of transistors of a first conductivity type having a channel region containing an impurity which increases a voltage threshold of said plurality of transistors of said first conductivity type, each of said plurality of transistors of first conductivity type having substantially the same total impurity dose in said channel region, wherein said total impurity dose in said channel region of said plurality of transistors of said first conductivity type comprises a halo implant,

forming a blanket film covering said plurality of transistors of said first conductivity type,

removing one or more portions of said blanket film from at least one selected transistor of said plurality of transistors of said first conductivity type, and

diffusing an impurity from said channel region of transistors of said first conductivity type which are covered by remaining portions of said blanket film into material adjacent said channel region, whereby a voltage threshold of said plurality of transistors of said first conductivity type other than said at least one selected transistor is reduced, and wherein said diffusing step removes said halo implant from said channel region of said transistors of said first conductivity type which are covered by remaining portions of said blanket film,

wherein after said diffusing step, a total impurity dose in a channel region of a covered transistor of said plurality of transistors of a first conductivity type and material adjacent said channel region is substantially equal to a total impurity dose in a channel region of said at least one selected transistor from which said blanket film was removed but differently distributed.

2. The method as recited in claim 1, including the further steps of

forming a plurality of transistors of a second conductivity type,

forming a blanket film covering said plurality of transistors of said second conductivity type, and

removing one or more portions of said blanket film from at least one selected transistor of said plurality of transistors of said second conductivity type.

3. The method as recited in claim 2, wherein said step of removing one or more portions of said blanket film from said at least one selected transistor of said plurality of transistors of said second conductivity type includes said step of removing one or more portions of said blanket film from said at least one selected transistor of said first conductivity type.

4. The method as recited in claim 2, wherein said plurality of transistors of said second conductivity type are NMOS transistors.

5. The method as recited in claim 1, wherein said plurality of transistors of said first conductivity type are NMOS transistors.

6. The method as recited in claim 1, wherein said step of diffusing an impurity includes diffusion of boron.

7. The method as recited in claim 1, wherein said step of forming a plurality of transistors of a first conductivity type includes forming transistors of different gate/channel lengths.

8. The method as recited in claim 2, wherein said step of forming a blanket film covering said plurality of transistors of said first conductivity type includes said step of forming a blanket film covering said plurality of transistors of said second conductivity type.

9. The method as recited in claim 1, wherein said step of forming a plurality of transistors of a first conductivity type includes forming transistors of equal gate/channel lengths.