Semiconductor device including metal-oxide-semiconductor field effect transistors and methods of fabricating the same

• US 8,927,367 B2
• Filed: 01/08/2013
• Issued: 01/06/2015
• Est. Priority Date: 02/27/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Urazaev, Vladimir, Jeong, Jin Ha, Lee, Changhun, Jeong, Yongsang
• Primary Examiner(s): Geyer, Scott B
• Application Number:
  US13/736,457
• Publication Number:
  US 20130224920A1
• Time in Patent Office: 728 Days
• Field of Search: None
• US Class Current: 438/270
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A method of fabricating a semiconductor device may include patterning a substrate to form trenches, forming a sacrificial layer to cover inner surfaces of the trenches, the sacrificial layer having a single-layered structure, forming sacrificial patterns by isotropically etching the sacrificial layer such that the sacrificial layer remains on bottom surfaces of the trenches, forming lightly doped regions in sidewalls of the trenches using the sacrificial patterns as an ion mask, removing the sacrificial patterns, and sequentially forming a gate insulating layer and a gate electrode layer in the trenches.

Claims

1. A method of fabricating a semiconductor device, comprising:

patterning a substrate to form trenches;

forming a sacrificial layer to cover inner surfaces of the trenches, the sacrificial layer having a single-layered structure;

forming sacrificial patterns by isotropically etching the sacrificial layer such that the sacrificial layer remains on bottom surfaces of the trenches;

forming lightly doped regions in sidewalls of the trenches using the sacrificial patterns as an ion mask;

removing the sacrificial patterns; and

sequentially forming a gate insulating layer and a gate electrode layer in the trenches.

2. The method of claim 1, wherein the forming a sacrificial layer forms the sacrificial layer having a greater thickness on the bottom surfaces of the trenches than on the sidewalls of the trenches.

3. The method of claim 1, wherein the forming a sacrificial layer forms the sacrificial layer at least two times thicker on the bottom surfaces of the trenches than on the sidewalls of the trenches.

4. The method of claim 1, wherein the forming a sacrificial layer forms the sacrificial layer using a physical vapor deposition process.

5. The method of claim 1, wherein the patterning a substrate to form trenches includes patterning the substrate to form first and second trenches having different depths from each other,

wherein the forming sacrificial patterns includes forming first and second sacrificial patterns on bottom surfaces of the first and second trenches, respectively, and

wherein a difference in thickness between the first and second sacrificial patterns is smaller than one-fourth of a difference in depth between the first and second trenches.

6. The method of claim 1, further comprising:

forming a buffer layer to cover the inner surfaces of the trenches before the forming a sacrificial layer; and

removing the buffer layer to expose the inner surfaces of the trenches after the removing the sacrificial patterns.

7. The method of claim 6, wherein the forming a buffer layer forms a silicon oxide layer, and the forming a sacrificial layer forms a material having an etch selectivity with respect to the buffer layer.

8. The method of claim 1, before the sequentially forming a gate insulating layer and a gate electrode layer in the trenches, further comprising:

forming electrode separation patterns remaining locally on upper sidewalls of the trenches, respectively.

9. The method of claim 8, wherein the forming electrode separation patterns comprises:

forming a trench insulating layer to fill the trenches after the removing the sacrificial patterns;

patterning an upper portion of the trench insulating layer to form gaps spaced apart from the lightly doped regions;

forming spacers on sidewalls of the gaps; and

removing a lower portion of the trench insulating layer using the spacers.

10. The method of claim 1, after the sequentially forming a gate insulating layer and a gate electrode layer in the trenches, further comprising:

forming heavily doped regions in an upper region of the substrate to be connected to the lightly doped regions.

11. The method of claim 1, wherein the removing the sacrificial patterns includes laterally etching the sidewalls of the trenches exposed by the sacrificial patterns, such that a width of the trenches decreases in a downward vertical direction from the sacrificial patterns.

12. A method of fabricating a semiconductor device, comprising:

forming a sacrificial layer to cover inner surfaces and a bottom surface of trenches formed in a substrate;

forming sacrificial patterns by isotropically etching the sacrificial layer such that the sacrificial layer remains on bottom surfaces of the trenches;

forming lightly doped regions on the exposed inner surfaces of the trenches;

removing the sacrificial patterns; and

sequentially forming a gate insulating layer and a gate electrode layer in the trenches.

13. The method of claim 12, wherein the forming lightly doped regions includes using the sacrificial patterns as an ion mask.

14. The method of claim 12, wherein forming a sacrificial layer forms the sacrificial layer having a single-layered structure.

15. The method of claim 12, wherein the forming a sacrificial layer forms the sacrificial layer having a greater thickness on the bottom surfaces of the trenches than on the inner surfaces of the trenches.

16. The method of claim 12, wherein the forming a sacrificial layer forms the sacrificial layer at least two times thicker on the bottom surfaces of the trenches than on the inner surfaces of the trenches.

17. The method of claim 12, wherein the forming a sacrificial layer forms the sacrificial layer using a physical vapor deposition process.

18. The method of claim 12, further comprising:

forming a buffer layer to cover the inner surfaces of the trenches before the forming a sacrificial layer; and

removing the buffer layer to expose the inner surfaces of the trenches after the removing the sacrificial patterns.

19. The method of claim 18, wherein the forming a buffer layer forms a silicon oxide layer, and the forming a sacrificial layer forms a material having an etch selectivity with respect to the buffer layer.