Method of forming a trench gate MOSFET having a thick bottom oxide

• US 8,927,369 B2
• Filed: 03/08/2013
• Issued: 01/06/2015
• Est. Priority Date: 07/13/2012
• Status: Active Grant

• Current Assignee: uPI Semiconductor Corporation
• Original Assignee: UBIQ Semiconductor Corp.
• Inventors: Chan, Chien-Ling, Lee, Chi-Hsiang
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): PATERSON, BRIGITTE A
• Application Number:
  US13/789,692
• Publication Number:
  US 20140017864A1
• Time in Patent Office: 669 Days
• Field of Search: None
• US Class Current: 438/272
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench.

Claims

1. A method of forming a trench gate MOSFET, comprising:

forming an epitaxial layer with a first conductivity type on a substrate with the first conductivity type;

forming a trench in the epitaxial layer;

conformally forming a first insulating layer and a first conductive layer on surfaces of the epitaxial layer and the trench;

filling up the trench with a second insulating layer;

removing a portion of the first conductive layer to form a second conductive layer below the second insulating layer;

removing the second insulating layer and a portion of the first insulating layer to form a third insulating layer below the second conductive layer;

performing an oxidation process to oxidize the second conductive layer to a fourth insulating layer, wherein a fifth insulating layer is simultaneously formed on the surface of the epitaxial layer and on a sidewall of the trench by the oxidation process;

forming a third conductive layer in the trench;

forming two body layers with a second conductivity type in the epitaxial layer respectively beside the trench; and

forming two doped regions with the first conductivity type in the body layers respectively beside the trench.

2. The method of forming the trench gate MOSFET as recited in claim 1, wherein a method of forming the second insulating layer comprises:

forming an insulating material layer on the epitaxial layer, and the insulating material layer filling up the trench; and

performing an etching back process to remove a portion of the insulating material layer.

3. The method of forming the trench gate MOSFET as recited in claim 1, wherein a method of forming the second conductive layer comprises using the second insulating layer as a mask to perform an anisotropic dry etching process.

4. The method of forming the trench gate MOSFET as recited in claim 1, wherein a method of forming the third insulating layer comprises using the second conductive layer as a mask to perform an anisotropic dry etching process.

5. The method of forming the trench gate MOSFET as recited in claim 1, wherein the method of forming the third conductive layer comprises:

forming a conductive material layer on the epitaxial layer, and the conductive material layer filling up the trench; and

performing an etching back process to remove a portion of the conductive material layer.

6. The method of forming the trench gate MOSFET as recited in claim 1, further comprising, after the step of performing the oxidation process and before the step of forming the third conductive layer:

removing the fifth insulating layer and a portion of the fourth insulating layer; and

forming a sixth insulating layer on the surfaces of the epitaxial layer and the trench.

7. The method of forming the trench gate MOSFET as recited in claim 1, further comprising, after the step of forming the doped regions:

forming a dielectric layer on the third conductive layer and the doped regions;

forming two openings penetrating the dielectric layer and the doped regions; and

forming a fourth conductive layer on the dielectric layer, wherein the fourth conductive layer fills in the openings to be electrically connected to the body layers.

8. The method of forming the trench gate MOSFET as recited in claim 7, wherein a material of the fourth conductive layer comprises metal.

9. The method of forming the trench gate MOSFET as recited in claim 1, wherein a material of the first conductive layer comprises undoped polysilicon.

10. The method of forming the trench gate MOSFET as recited in claim 1, wherein a material of the third conductive layer comprises doped polysilicon.

11. The method of forming the trench gate MOSFET as recited in claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type;

or the first conductivity type is P-type and the second conductivity type is N-type.