Method for manufacturing deep-trench super PN junctions

• US 8,927,386 B2
• Filed: 05/31/2012
• Issued: 01/06/2015
• Est. Priority Date: 06/08/2011
• Status: Active Grant

• Current Assignee: CSMC Technologies FAB1 Company Limited (CSMC Manufacturing Company Limited)
• Original Assignee: CSMC Technologies FAB1 Company Limited (CSMC Manufacturing Company Limited)
• Inventors: Wu, Tzong Shiann, Wang, Genyi, Yuan, Leibing, Wu, Pengpeng
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Perkins, Pamela E
• Application Number:
  US13/878,453
• Publication Number:
  US 20130196489A1
• Time in Patent Office: 950 Days
• Field of Search: None
• US Class Current: 438/416
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/66136 PN junction diodes

Abstract

The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.

Claims

1. A method for forming a super PN junction, comprising:

a deposition step for forming an epitaxial layer on a substrate;

a dielectric forming step for forming of a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer;

a deep trench forming step for forming deep trenches in the epitaxial layer;

a first filling step before removing the second dielectric layer for completely filling the deep trenches and beyond the second dielectric layer with an epitaxial material;

a second filling step for forming a surface filling layer with a predetermined thickness by filling an entire surface including the second dielectric layer and the epitaxial material, using a third dielectric, wherein the third dielectric is SOG;

an etching step for etching back the surface filling layer and the epitaxial material to expose an interface of the first dielectric layer and the epitaxial layer on the substrate; and

a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize the epitaxial layer.

2. The super-PN-junction forming method according to claim 1, wherein:

the etching process is a plasma etching process.

3. The super-PN-junction forming method according to claim 2, wherein:

the plasma etching process adjusts an etching rate selectivity ratio to obtain an etching rate selectivity ratio of 1;

1 for the epitaxial material and the third dielectric.

4. The super-PN-junction forming method according to claim 3, wherein:

the first dielectric is oxide and the second dielectric is nitride.

5. The super-PN-junction forming method according to claim 2, wherein:

in the second filling process, the third dielectric is filled by an accessary equipment and the third dielectric is a flowable dielectric.

6. The super-PN-junction forming method according to claim 5, wherein:

a height of the surface filling layer is at least higher than a highest point of the epitaxial material.

7. The super-PN-junction forming method according to claim 6, wherein:

the first dielectric is oxide and the second dielectric is nitride.

8. The super-PN-junction forming method according to claim 5, wherein:

in the second filling process, the flowable third dielectric completely fills an entire surface of the second dielectric and the epitaxial material using a spin-coating process.

9. The super-PN-junction forming method according to claim 8, wherein:

the first dielectric is oxide and the second dielectric is nitride.

10. The super-PN-junction forming method according to claim 5, wherein:

a wet process is used to remove the first dielectric layer, the second dielectric layer, and the surface filling layer.

11. The super-PN-junction forming method according to claim 10, wherein:

the first dielectric is oxide and the second dielectric is nitride.

12. The super-PN-junction forming method according to claim 5, wherein:

in the first filling process, a lowest point of the epitaxial material is higher than the interface of the first dielectric and the epitaxial layer on the substrate.

13. The super-PN-junction forming method according to claim 12, wherein:

the first dielectric is oxide and the second dielectric is nitride.

14. The super-PN-junction forming method according to claim 5, wherein:

the first dielectric is oxide and the second dielectric is nitride.

15. The super-PN-junction forming method according to claim 2, wherein:

the first dielectric is oxide and the second dielectric is nitride.

16. The super-PN-junction forming method according to claim 1, wherein:

the first dielectric is oxide and the second dielectric is nitride.

17. The super-PN-junction forming method according to claim 16, wherein:

a thickness of the first dielectric is greater than 500Å

, and a thickness of the second dielectric is greater than 300Å

.

18. A method for forming a super PN junction, comprising:

a deposition step for forming an epitaxial layer on a substrate;

a dielectric forming step for forming of a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer;

a deep trench forming step for forming deep trenches in the epitaxial layer;

a first filling step for completely filling the deep trenches and beyond the second dielectric layer with an epitaxial material;

a second filling step for forming a surface filling layer with a predetermined thickness by filling an entire surface including the second dielectric layer and the epitaxial material, using a third dielectric;

an etching step for etching back the surface filling layer to expose an interface of the first dielectric layer and the epitaxial layer on the substrate, wherein the etching process is a plasma etching process that adjusts an etching rate selectivity ratio to obtain an etching rate selectivity ratio of 1;

1 for the epitaxial material and the third dielectric; and

a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize the epitaxial layer.

19. A method for forming a super PN junction, comprising:

a deposition step for forming an epitaxial layer on a substrate;

a dielectric forming step for forming of a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer;

a deep trench forming step for forming deep trenches in the epitaxial layer;

a first filling step for completely filling the deep trenches and beyond the second dielectric layer with an epitaxial material;

a second filling step for forming a surface filling layer with a predetermined thickness by filling an entire surface including the second dielectric layer and the epitaxial material, using a third dielectric, wherein the third dielectric is filled by an accessary equipment and the third dielectric is a flowable dielectric that completely fills the entire surface of the second dielectric and the epitaxial material using a spin-coating process;

an etching step for etching back the surface filling layer to expose an interface of the first dielectric layer and the epitaxial layer on the substrate; and

a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize the epitaxial layer.