Trench Schottky diode and method for manufacturing the same

• US 8,927,401 B2
• Filed: 01/07/2013
• Issued: 01/06/2015
• Est. Priority Date: 06/26/2009
• Status: Active Grant

• Current Assignee: PFC Device Holdings Ltd. (PFC Device, Inc.)
• Original Assignee: PFC Device Corp. (PFC Device, Inc.)
• Inventors: Chao, Kou-Liang, Kuo, Hung-Hsin, Su, Tse-Chuan, Chen, Mei-Ling
• Primary Examiner(s): STARK, JARRETT J
• Application Number:
  US13/735,176
• Publication Number:
  US 20130122695A1
• Time in Patent Office: 729 Days
• Field of Search: 438/576, 438/578, 438/579
• US Class Current: 438/576
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.

Claims

1. A method for manufacturing a trench Schottky diode, comprising steps of:

providing a semiconductor substrate having a first surface;

forming a first mask layer on the first surface, wherein the first mask layer includes a first plurality of openings and a second plurality of opening;

forming a first plurality of trenches and a second plurality of trenches in the semiconductor substrate according to the first mask layer;

forming a first plurality of gate oxide layers correspondingly formed on surfaces of the first plurality of trenches and a second plurality of gate oxide layers correspondingly formed on surfaces of the second plurality of trenches, wherein the first plurality of gate oxide layers and the second plurality of gate oxide layers protrude above the first surface of the semiconductor substrate;

filling a first plurality of polysilicon structures in the first plurality of trenches and a second plurality of polysilicon structures in the second plurality of trenches, wherein the first plurality of polysilicon structures and the second plurality of polysilicon structures protrude above the first surface of the semiconductor substrate;

forming a second mask layer covering mask layer, the first plurality of polysilicon structures and the second plurality of polysilicon structures;

removing a portion of the first mask layer and a portion of the second mask layer, wherein a remained portion of the first mask layer is on a portion of the first surface among the first plurality of trenches and covers the first surface among the first plurality of trenches and the first plurality of gate oxide layers, and wherein a remained portion of the second mask layer is on the remained portion of the first mask layer and the first plurality of polysilicon structures, and completely covers the remained portion of the first mask layer; and

forming an electrode on the other portion of the first surface, the remained portion of the second mask layer, the second plurality of the protruding polysilicon structures and the second plurality of the protruding gate oxide layers.

2. The method according to claim 1 wherein the semiconductor substrate comprises a relatively heavily-doped silicon substrate and a relatively lightly-doped epitaxial layer wherein the first plurality of trenches and the second plurality of trenches are formed in the relatively lightly-doped epitaxial layer.

3. The method according to claim 1 wherein the step of forming the first plurality of trenches and the second plurality of trenches further comprises steps of:

forming the first mask layer on the first surface, wherein the first mask layer includes the first plurality of openings and the second plurality of openings; and

etching the semiconductor substrate according to the first plurality of openings and the second plurality of openings of the first mask layer to form the first plurality of trenches and the second plurality of trenches in the semiconductor substrate.

4. The method according to claim 3 wherein the first mask layer is a silicon oxide layer formed by performing a thermal oxidation process or a chemical vapor deposition (CVD) process.

5. The method according to claim 1 wherein before the step of forming the first plurality of gate oxide layers and the second plurality of gate oxide layers, further comprises steps of:

etching surfaces of the first plurality of trenches and the second plurality of trenches to smooth the surfaces of the first plurality of trenches and the second plurality of trenches;

forming a sacrificial oxide layer on the smooth surfaces of the first plurality of trenches and the second plurality of trenches; and

removing the sacrificial layer.

6. The method according to claim 1 wherein the first plurality of polysilicon structures and the second plurality of polysilicon structures are formed by a CVD process.

7. The method according to claim 1, further comprising a step of implanting boron or phosphorous ions into the first plurality of polysilicon structures and the second plurality of polysilicon structures.

8. The method according to claim 1 wherein the second mask layer is a protective layer made of a borophosphosilicate glass (BPSG) layer formed by a CVD process.

9. The method according to claim 1 wherein the step of forming the electrode comprises steps of:

performing a first metal sputtering process on the other portion of the first surface, the remained portion of the second mask layer, the second plurality of the protruding polysilicon structures and the second plurality of the protruding gate oxide layers to form a first metal layer;

performing a second metal sputtering process on the first metal layer to form a second metal layer; and

removing a portion of the first metal layer and the second metal layer on the remained portion of the second mask layer to form the electrode.

10. The method according to claim 9 wherein the first metal layer is made of titanium (Ti), and the second metal layer is made of an alloy of aluminum, silicon and copper (Al/Si/Cu).

11. The method according to claim 9, further comprises a rapid thermal processing (RTP) step after the first metal sputtering process or the second metal sputtering process.

12. The method according to claim 9, further comprises a sintering process after the second metal sputtering process to enhance adhesion of the electrode to the remained portion of the second mask layer.