Semiconductor device and method for manufacturing the same

• US 8,927,981 B2
• Filed: 03/17/2010
• Issued: 01/06/2015
• Est. Priority Date: 03/30/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Akimoto, Kengo, Godo, Hiromichi, Miyanaga, Akiharu
• Primary Examiner(s): Gebremariam, Samuel
• Assistant Examiner(s): Bell, Lauren R
• Application Number:
  US12/725,478
• Publication Number:
  US 20100244031A1
• Time in Patent Office: 1,756 Days
• Field of Search: 438/158, 438/151, 438/104, 438/149, 257/23, 257/43, 257/57, 257/E21.414, 257/E21.413, 257/E29.296, 257/E29.273, 257/72, 257/350, 257/61
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The drain voltage of a transistor is determined depending on the driving voltage of an element connected to the transistor. With downsizing of a transistor, intensity of the electric field concentrated in the drain region is increased, and hot carriers are easily generated. An object is to provide a transistor in which the electric field hardly concentrates in the drain region. Another object is to provide a display device including such a transistor. End portions of first and second wiring layers having high electrical conductivity do not overlap with a gate electrode layer, whereby concentration of an electric field in the vicinity of a first electrode layer and a second electrode layer is reduced; thus, generation of hot carriers is suppressed. In addition, one of the first and second electrode layers having higher resistivity than the first and second wiring layers is used as a drain electrode layer.

Claims

1. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating film over the gate electrode;

a first electrode and a second electrode over the gate insulating film;

a first wiring over the first electrode;

a second wiring over the second electrode;

an oxide semiconductor layer over the first wiring and the second wiring, the oxide semiconductor layer being in contact with a side face and a top face of each of the first electrode and the second electrode and a side face and a top face of each of the first wiring and the second wiring; and

a protective insulating layer over the oxide semiconductor layer,

wherein the first electrode is extended so as to have an end portion positioned more inwardly than an end portion of the first wiring and overlap with the gate electrode, and the second electrode is extended so as to have an end portion positioned more inwardly than an end portion of the second wiring and overlap with the gate electrode,

wherein the first wiring and the second wiring do not overlap with the gate electrode,

wherein electrical conductivity of each of the first electrode and the second electrode is equal to or higher than electrical conductivity of the oxide semiconductor layer,

wherein electrical conductivity of the first electrode is equal to or lower than electrical conductivity of the first wiring,

wherein electrical conductivity of the second electrode is equal to or lower than electrical conductivity of the second wiring, and

wherein the protective insulating layer has direct contact with the gate insulating film, the first wiring, the second wiring, and the oxide semiconductor layer without having direct contact with any portion of the first electrode and the second electrode.

2. The semiconductor device according to claim 1, wherein the end portion of the first wiring is aligned with one end portion of the gate electrode, and wherein the end portion of the second wiring is aligned with the other end portion of the gate electrode.

3. The semiconductor device according to claim 1, wherein a thickness of the oxide semiconductor layer is within the range of from 5 nm to 200 nminclusive, and wherein a thickness of each of the first electrode and the second electrode is within the range of from 5 nm to 200 nm inclusive.

4. The semiconductor device according to claim 1, wherein electrical conductivity of each of the first electrode and the second electrode is within the range of from 1×

10<sup>−

4</sup> S/cm to 1×

10² S/cm inclusive.

5. The semiconductor device according to claim 1, wherein a length of a region where the first electrode overlaps with the gate electrode and a length of a region where the second electrode overlaps with the gate electrode are each within the range of from 0.2 μ

m to 5 μ

m inclusive.

6. The semiconductor device according to claim 1,

wherein each of the first electrode and the second electrode comprises indium, gallium, and zinc, and

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

7. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating film overlapping with the gate electrode;

a first electrode and a second electrode overlapping with the gate insulating film;

a first wiring overlapping with the first electrode;

a second wiring overlapping with the second electrode;

an oxide semiconductor layer over the first wiring and the second wiring, the oxide semiconductor layer being in contact with a side face and a top face of each of the first electrode and the second electrode and a side face and a top face of each of the first wiring and the second wiring; and

a protective insulating layer over the oxide semiconductor layer,

wherein the first electrode is extended so as to have an end portion positioned more inwardly than an end portion of the first wiring and overlap with the gate electrode, and the second electrode is extended so as to have an end portion positioned more inwardly than an end portion of the second wiring and overlap with the gate electrode,

wherein the first wiring and the second wiring do not overlap with the gate electrode,

wherein electrical conductivity of each of the first electrode and the second electrode is equal to or higher than electrical conductivity of the oxide semiconductor layer,

wherein electrical conductivity of the first electrode is equal to or lower than electrical conductivity of the first wiring,

wherein electrical conductivity of the second electrode is equal to or lower than electrical conductivity of the second wiring, and

wherein the protective insulating layer has direct contact with the gate insulating film, the first wiring, the second wiring, and the oxide semiconductor layer without having direct contact with any portion of the first electrode and the second electrode.

8. The semiconductor device according to claim 7, wherein the end portion of the first wiring is aligned with one end portion of the gate electrode, and wherein the end portion of the second wiring is aligned with the other end portion of the gate electrode.

9. The semiconductor device according to claim 7, wherein a thickness of the oxide semiconductor layer is within the range of from 5 nm to 200 nm inclusive, and wherein a thickness of each of the first electrode and the second electrode is within the range of from 5 nm to 200 nm inclusive.

10. The semiconductor device according to claim 7, wherein electrical conductivity of each of the first electrode and the second electrode is within the range of from 1×

10<sup>−

4</sup> S/cm to 1×

10² S/cm inclusive.

11. The semiconductor device according to claim 7, wherein a length of a region where the first electrode overlaps with the gate electrode and a length of a region where the second electrode overlaps with the gate electrode are each within the range of from 0.2 μ

m to 5 μ

m inclusive.

12. The semiconductor device according to claim 7,

wherein each of the first electrode and the second electrode comprises indium, gallium, and zinc, and

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

13. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating film overlapping with the gate electrode;

a first electrode and a second electrode overlapping with the gate insulating film;

a first wiring overlapping with the first electrode;

a second wiring overlapping with the second electrode;

an oxide semiconductor layer over the first wiring and the second wiring, the oxide semiconductor layer being in contact with a side face and a top face of each of the first electrode and the second electrode and a side face and a top face of each of the first wiring and the second wiring; and

a protective insulating layer over the oxide semiconductor layer,

wherein the first electrode is extended so as to have an end portion positioned more inwardly than an end portion of the first wiring and overlap with the gate electrode, and the second electrode is extended so as to have an end portion positioned more inwardly than an end portion of the second wiring and overlap with the gate electrode,

wherein the first wiring and the second wiring do not overlap with the gate electrode, and

wherein the protective insulating layer has direct contact with the gate insulating film, the first wiring, the second wiring, and the oxide semiconductor layer without having direct contact with any portion of the first electrode and the second electrode.

14. The semiconductor device according to claim 13, wherein the end portion of the first wiring is aligned with one end portion of the gate electrode, and wherein the end portion of the second wiring is aligned with the other end portion of the gate electrode.

15. The semiconductor device according to claim 13, wherein a thickness of the oxide semiconductor layer is within the range of from 5 nm to 200 nm inclusive, and wherein a thickness of each of the first electrode and the second electrode is within the range of from 5 nm to 200 nm inclusive.

16. The semiconductor device according to claim 13, wherein a length of a region where the first electrode overlaps with the gate electrode and a length of a region where the second electrode overlaps with the gate electrode are each within the range of from 0.2 μ

m to 5 μ

m inclusive.

17. The semiconductor device according to claim 13,

wherein each of the first electrode and the second electrode comprises indium, gallium, and zinc, and

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.