Heterostructure power transistor with AlSiN passivation layer

• US 8,928,037 B2
• Filed: 02/28/2013
• Issued: 01/06/2015
• Est. Priority Date: 02/28/2013
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Ramdani, Jamal, Murphy, Michael, Edwards, John Paul
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Smith, Stephen C
• Application Number:
  US13/780,192
• Publication Number:
  US 20140239309A1
• Time in Patent Office: 677 Days
• Field of Search: 257/192, 257/194, 257/E29.246, 257/E29.252
• US Class Current: 257/192
• CPC Class Codes: H01L 21/02107 Forming insulating materials on a substrate
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

Claims

1. A heterostructure power transistor comprising:

a first active layer,

a second active layer disposed on the first active layer, a two-dimensional electron gas layer forming between the first and second active layers;

a passivation/gate dielectric layer comprising aluminum silicon nitride (AlSiN) disposed on the second active layer;

an AlN layer disposed above the passivation/gate dielectric layer;

a gate;

a second gate dielectric layer disposed on the AlN layer, the gate being disposed above the second gate dielectric layer;

first and second ohmic contacts that electrically connect to the second active layer, the first and second ohmic contacts being laterally spaced-apart, the gate being disposed between the first and second ohmic contacts.

2. The heterostructure power transistor of claim 1 wherein the second gate dielectric layer comprises aluminum oxide (Al₂O₃).

3. The heterostructure power transistor of claim 1 further comprising an upper passivation layer disposed over the second gate dielectric layer, the gate extending vertically through the upper passivation layer to contact the second gate dielectric layer.

4. The heterostructure power transistor of claim 1 wherein the passivation/gate dielectric layer has a first thickness and the second gate dielectric has a second thickness, the second thickness being larger than the first thickness.

5. The heterostructure power transistor of claim 1 wherein the first and second ohmic contacts extend vertically through the second gate dielectric layer and the passivation/gate dielectric layer.

6. The heterostructure power transistor of claim 3 wherein the first and second ohmic contacts extend vertically through the upper passivation layer, the second gate dielectric layer, and the passivation/gate dielectric layer.

7. The heterostructure power transistor of claim 1 wherein the passivation/gate dielectric layer has a first thickness in a range of about 1-5 nanometers thick.

8. The heterostructure power transistor of claim 1 wherein the second gate dielectric has a second thickness in a range of about 10-20 nanometers thick.

9. The heterostructure power transistor of claim 1 wherein the first and second ohmic contacts respectively comprise source and drain ohmic contacts.

10. The heterostructure power transistor of claim 3 wherein the upper passivation layer comprises SiN.

11. The heterostructure power transistor according to claim 1 wherein the first active layer comprises gallium nitride (GaN).

12. The heterostructure power transistor of claim 1 wherein the second active layer comprises aluminum gallium nitride (AlGaN).

13. The heterostructure power transistor of claim 1 wherein the first and second active layers are defined as an isolated mesa.

22. The heterostructure power transistor of claim 1, wherein the aluminum silicon nitride (AlSiN) has an integrated nitrogen composition that is at stoichiometry between Si₃N₄ and AlN.

23. The heterostructure power transistor of claim 1 wherein the aluminum silicon nitride (AlSiN) has substantially 5-10% of aluminum (Al) to silicon nitride (SiN).

14. A method of fabricating a heterostructure semiconductor device comprising:

forming a first active layer on a substrate;

forming a second active layer on the first active layer, the first active layer and the second active layer having different bandgaps such that a two-dimensional electron gas layer is formed therebetween;

forming a passivation/gate dielectric layer comprising aluminum silicon nitride (AlSiN) on the second active layer, the passivation/gate dielectric layer having a first thickness, wherein the forming of the passivation/gate dielectric layer comprises growing in-situ with the AlSiN layer an AlN layer on top of the AlSiN layer;

forming a second gate dielectric layer of aluminum oxide over the passivation/gate dielectric layer using the AlN layer as a seed layer;

forming first and second ohmic contacts that each extend vertically through the passivationfgate dielectric layer, the first and second ohmic contacts being laterally spaced-apart and electrically connected to the second active layer; and

forming a gate at a lateral position between the first and second ohmic contacts.

15. The method of claim 14 wherein the second gate dielectric layer has a second thickness greater than the first thickness.

16. The method of claim 15 further comprising depositing an upper passivation layer over the second gate dielectric layer.

17. The method of claim 14 wherein the first active layer comprises gallium nitride.

18. The method of claim 14 wherein the second active layer comprises aluminum gallium nitride.

19. The method of claim 14 wherein the passivation/gate dielectric layer is formed in-situ with the first and second active layers.

20. The method of claim 14 wherein forming the passivation/gate dielectric layer comprising aluminum silicon nitride (AlSiN) comprises growing the aluminum silicon nitride (AlSiN) with an integrated nitrogen composition that is at stoichiometry between Si₃N₄ and AlN.

21. The method of claim 14 wherein forming the passivationfgate dielectric layer comprising aluminum silicon nitride (AlSiN) comprises forming the aluminum silicon nitride (AlSiN) with substantially 5-10% of aluminum (Al) to silicon nitride (SiN).