Trench DMOS device with improved termination structure for high voltage applications

• US 8,928,065 B2
• Filed: 10/21/2010
• Issued: 01/06/2015
• Est. Priority Date: 03/16/2010
• Status: Active Grant

• Current Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Original Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Inventors: Hsu, Chih-Wei, Udrea, Florin, Lin, Yih-Yin
• Primary Examiner(s): GEBREMARIAM, SAMUEL A
• Application Number:
  US12/909,033
• Publication Number:
  US 20110227152A1
• Time in Patent Office: 1,538 Days
• Field of Search: 257328-334
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.

Claims

1. A termination structure for a power transistor, said termination structure comprising:

a semiconductor substrate having an active region and a termination region, the substrate having a first type of conductivity;

a termination trench located in the termination region and extending from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate;

a doped region having a second type of conductivity disposed in the substrate below the termination trench;

a MOS gate formed on a sidewall adjacent the boundary, wherein the doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench;

a termination structure oxide layer formed on the termination trench covering a portion of the MOS gate and extending toward the edge of the substrate, the termination structure oxide layer and the doped region being in contact with one another and defining an interface therebetween;

a first conductive layer formed on a backside surface of the semiconductor substrate; and

a second conductive layer formed atop the active region, an exposed portion of the MOS gate, and extending to cover at least a portion of the termination structure oxide layer.

2. The termination structure of claim 1 further comprising a plurality of trench MOS devices spaced from each other and formed in the active region of the semiconductor substrate.

3. The termination structure of claim 1, wherein said MOS gate comprises a conductive layer and a gate oxide layer formed between a bottom of the termination trench and the conductive layer.

4. The termination structure of claim 1, wherein said trench MOS device is a Schottky diode.

5. The termination structure of claim 4, wherein said Schottky diode is a TMBS Schottky diode that includes at least one trench in the active region of the substrate.

6. The termination structure of claim 1, wherein said power transistor is a device selected from the group consisting of Schottky diodes, DMOSs, and IGBTs.

7. The termination structure of claim 1, further comprising one or more segmented metal regions located on the termination structure oxide layer and spaced apart from the second conductive layer.

8. The termination structure of claim 1, wherein the doped region is formed by implantation or diffusion.

9. The termination structure of claim 1, wherein the doped region is formed by implantation with an implantation dosage of between about 1×

10¹¹ atoms/cm² to 1×

10¹³ atoms/cm².

10. A Schottky diode, comprising:

a semiconductor substrate having a plurality of trench MOS devices spaced from each other formed in an active region of the semiconductor substrate, the substrate having a first type of conductivity;

a termination trench located in a termination region and extending from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate;

a doped region having a second type of conductivity disposed in the substrate below the termination trench;

a MOS gate formed on a sidewall adjacent the boundary, wherein the doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench;

a termination structure oxide layer formed on the termination trench covering a portion of the MOS gate and extending toward the edge of the substrate, the termination structure oxide layer and the doped region being in contact with one another and defining an interface therebetween;

a first conductive layer formed on a backside surface of the semiconductor substrate;

a second conductive layer formed atop the active region to define one or more Schottky barriers with one or more portions of the substrate located between adjacent ones of the trench MOS devices; and

a field plate extending over an exposed portion of the MOS gate and at least a portion of the termination structure oxide layer.

11. The Schottky diode of claim 10 wherein said field plates includes an extension of the second conductive layer into or over the termination trench.

12. The Schottky diode of claim 10, wherein said semiconductor substrate comprises a first layer and a base substrate, and said first layer has a first type of conductive impurities lightly doped and said base substrate has said first type of conductive impurities heavily doped.

13. The Schottky diode of claim 12, wherein said trench MOS devices and said termination trench are formed in said first layer having a depth of between about 1-15 microns.

14. The Schottky diode of claim 13, wherein said termination trench has a width between about 10-200 microns.

15. The Schottky diode of claim 10, wherein said termination trench is formed from the boundary of the active region and extends to within a certain distance of an edge of the semiconductor substrate, so that said termination trench has at least one sidewall.

16. The Schottky diode of claim 10 wherein said trench MOS devices and said MOS gate include a material selected from the group consisting of metal, polysilicon, and amorphous silicon.

17. The Schottky diode of claim 10, further comprising one or more segmented metal regions located on the termination structure oxide layer and spaced apart from the field plate.

18. The Schottky diode of claim 17, further comprising at least two segmented metal regions spaced apart from one another by between about 0.3 and 50 microns.