Three dimensional structure memory

• US 8,928,119 B2
• Filed: 03/17/2009
• Issued: 01/06/2015
• Est. Priority Date: 04/04/1997
• Status: Expired due to Fees

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: Elm 3DS Innovations LLC
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): CHIU, TSZ K
• Application Number:
  US12/405,240
• Publication Number:
  US 20090218700A1
• Time in Patent Office: 2,121 Days
• Field of Search: 257/777, 257/778, 257/E21.597, 257/E27.026, 257/E27.097, 257/254, 257/417, 257/419, 257/418, 257/619, 257/E21.564, 257/E23.169, 257/E21.545, 438/109, 438/455, 438/598
• US Class Current: 257/619
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A stacked integrated circuit comprising:

a plurality of substantially flexible integrated circuits having topside and bottom-side surfaces, wherein said integrated circuits are stacked in relation to one another, wherein at least one of the substantially flexible integrated circuits comprises a substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned by at least one of abrasion, etching and parting to expose a surface, and subsequently polishing or smoothing the exposed surface to form a polished or smoothed surface; and

interconnections that pass through one or more of the plurality of substantially flexible integrated circuits and that electrically connect the plurality of substantially flexible integrated circuits, wherein the interconnections are vertical interconnections and are internal to the plurality of substantially flexible integrated circuits.

2. The stacked integrated circuit of claim 1, wherein at least one of the plurality of substantially flexible integrated circuits comprises a low stress dielectric material.

3. The stacked integrated circuit of claim 2, wherein the low stress dielectric material is at least one of a silicon-based dielectric material, a silicon dioxide dielectric material, and an oxide of silicon dielectric material and has a stress of less than 5×

10⁸ dynes/cm² tensile.

4. The stacked integrated circuit of claim 1, wherein at least two of:

at least one of the substantially flexible integrated circuits comprises dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile;

the dielectric material is at least one of silicon dioxide and an oxide of silicon;

at least one of the substantially flexible integrated circuits has one of logic circuitry and memory circuitry formed thereon;

at least one of the interconnections passes through the substantially flexible substrate and is insulated by an insulation material from said substrate, the insulation material comprising a silicon-based dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

5. The stacked integrated circuit of claim 1, wherein at least three of:

at least one of the substantially flexible integrated circuits comprises dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile;

the dielectric material is at least one of silicon dioxide and an oxide of silicon;

at least one of the substantially flexible integrated circuits has one of logic circuitry and memory circuitry formed thereon;

at least one of the interconnections passes through the substantially flexible substrate and is insulated by an insulation material from said substrate, the insulation material comprising a silicon-based dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

6. The stacked integrated circuit of claim 1, wherein at least four of:

at least one of the substantially flexible integrated circuits comprises dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile;

the dielectric material is at least one of silicon dioxide and an oxide of silicon;

at least one of the substantially flexible integrated circuits has one of logic circuitry and memory circuitry formed thereon;

at least one of the interconnections passes through the substantially flexible monocrystalline substrate and is insulated by an insulation material from said substrate, the insulation material comprising a silicon-based dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

7. The stacked integrated circuit of claim 1, wherein the substantially flexible substantially flexible monocrystalline semiconductor substrate has a silicon-based dielectric layer formed thereon with a stress of less than 5×

10⁸ dynes/cm² tensile.

8. The stacked integrated circuit of claim 7, wherein at least one of the plurality of substantially flexible integrated circuits has a thickness of 50 microns or less.

9. The stacked integrated circuit of claim 7, wherein at least one of the plurality of substantially flexible integrated circuits comprises a single crystal semiconductor material and wherein at least one of the plurality of substantially flexible integrated circuits comprises at least one memory array of memory cells.

10. The stacked integrated circuit of claim 7, wherein the plurality of substantially flexible integrated circuits comprises at least one of a logic integrated circuit and a memory integrated circuit.

11. The stacked integrated circuit of claim 10, wherein the logic integrated circuit is a microprocessor integrated circuit.

12. The stacked integrated circuit of claim 7, wherein the plurality of substantially flexible integrated circuits comprises a plurality of logic integrated circuits.

13. The stacked integrated circuit of claim 7, wherein at least two of the interconnections electrically interconnect at least two of the plurality of substantially flexible integrated circuits and are vertical interconnections passing through the substantially flexible monocrystalline semiconductor substrate and insulated by an insulation material from the substantially flexible monocrystalline semiconductor substrate, the insulation material comprising a silicon-based dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

14. The stacked integrated circuit of claim 7, wherein at least one of the interconnections passes vertically through the substantially flexible monocrystalline semiconductor substrate and is insulated by an insulation material from said substantially flexible monocrystalline semiconductor substrate, the insulation material comprising a silicon-based dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

15. The stacked integrated circuit of claim 7, wherein data processing is performed by at least two of the substantially flexible integrated circuits in cooperation with one another.

16. The stacked integrated circuit of claim 7, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

17. The stacked integrated circuit of claim 7, wherein said interconnections comprise a plurality of vertical interconnections passing through the substantially flexible monocrystalline semiconductor substrate, each of said vertical interconnections comprising a conductive center portion and an insulating portion surrounding the conductive center portion.

18. The stacked integrated circuit of claim 17, wherein the insulating portion surrounding the conductive center portion of said vertical interconnections comprises a dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

19. The stacked integrated circuit of claim 17, wherein at least one of the following:

the insulating portion surrounding the conductive center portion of said vertical interconnections comprises a dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile;

one of the substantially flexible integrated circuits is formed using a different process technology than another of the substantially flexible integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance;

at least one of substantially flexible integrated circuits comprises a microprocessor;

the substantially flexible integrated circuits comprise at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit;

a plurality of interior vertical interconnections traverse at least one of the substantially flexible integrated circuits;

continuous vertical interconnections connect circuitry of the substantially flexible integrated circuits;

information processing is performed on data routed between circuitry on the substantially flexible integrated circuits;

at least one substantially flexible integrated circuit has reconfiguration circuitry;

vertical interconnections connect the circuit substrate and circuitry of a first substantially flexible integrated circuit, each vertical interconnection comprising a conductive center portion and a insulating portion surrounding the conductive center portion, the insulating portion comprising a dielectric material having stress of less than 5×

10⁸ dynes/cm² tensile;

at least one of the substantially flexible integrated circuits comprises a dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile.

20. The stacked integrated circuit of claim 17, wherein at least two of the following:

the insulating portion surrounding the conductive center portion of said vertical interconnections comprises a dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile;

one of the substantially flexible integrated circuits is formed using a different process technology than another of the substantially flexible integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance;

at least one of substantially flexible integrated circuits comprises a microprocessor;

the substantially flexible integrated circuits comprise at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit;

a plurality of interior vertical interconnections traverse at least one of the substantially flexible integrated circuits;

continuous vertical interconnections connect circuitry of the substantially flexible integrated circuits;

information processing is performed on data routed between circuitry on the substantially flexible integrated circuits;

at least one substantially flexible integrated circuit has reconfiguration circuitry;

vertical interconnections connect the circuit substrate and circuitry of a first substantially flexible integrated circuit, each vertical interconnection comprising a conductive center portion and a insulating portion surrounding the conductive center portion, the insulating portion comprising a dielectric material having stress of less than 5×

10⁸ dynes/cm² tensile;

at least one of the substantially flexible integrated circuits comprises a dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile;

the stacked integrated circuit is a stacked integrated memory circuit, and wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit block stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks are configured to independently perform memory operations;

a plurality of the substantially flexible integrated circuits each comprises a deposited polysilicon layer and a low stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile;

the at least one of the substantially flexible integrated circuits is made flexible by the combination of

     1) thinning the semiconductor substrate to form a thinned surface,

     2) polishing or smoothing the thinned surface, and

     3) depositing over the semiconductor substrate one or more low stress silicon-based dielectric layers having a stress of less than 5×

10⁸ dynes/cm² tensile.

21. The stacked integrated circuit of claim 17, wherein at least three of the following:

the insulating portion surrounding the conductive center portion of said vertical interconnections comprises a dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile;

one of the substantially flexible integrated circuits is formed using a different process technology than another of the substantially flexible integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance;

at least one of substantially flexible integrated circuits comprises a microprocessor;

the substantially flexible integrated circuits comprise at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit;

a plurality of interior vertical interconnections traverse at least one of the substantially flexible integrated circuits;

continuous vertical interconnections connect circuitry of the substantially flexible integrated circuits;

information processing is performed on data routed between circuitry on the substantially flexible integrated circuits;

at least one substantially flexible integrated circuit has reconfiguration circuitry;

vertical interconnections connect the circuit substrate and circuitry of a first substantially flexible integrated circuit, each vertical interconnection comprising a conductive center portion and a insulating portion surrounding the conductive center portion, the insulating portion comprising a dielectric material having stress of less than 5×

10⁸ dynes/cm² tensile;

at least one of the substantially flexible integrated circuits comprises a dielectric layer with a stress of less than 5×

10⁸ dynes/cm² tensile;

the stacked integrated circuit is a stacked integrated memory circuit, and wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit block stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks are configured to independently perform memory operations;

a plurality of the substantially flexible integrated circuits each comprises a deposited polysilicon layer and a low stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile;

the at least one of the substantially flexible integrated circuits is made flexible by the combination of

     1) thinning the semiconductor substrate to form a thinned surface,

     2) polishing or smoothing the thinned surface, and

     3) depositing over the semiconductor substrate one or more low stress silicon-based dielectric layers having a stress of less than 5×

10⁸ dynes/cm² tensile.

22. The stacked integrated circuit of claim 7, wherein the stacked integrated circuit is a stacked integrated memory circuit, and wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of block stacks each comprising vertically interconnected circuit blocks on the integrated circuits, wherein the block stacks are configured to independently perform different memory accesses.

23. The stacked integrated circuit of claim 7, wherein said interconnections comprise at least one vertical interconnection, each vertical interconnection comprising a hole etched through the substantially flexible monocrystalline semiconductor substrate and within said hole a conductive center portion and an insulating portion surrounding the conductive center portion.

24. The stacked integrated circuit of claim 23, wherein the insulating portion comprises a low stress dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

25. The stacked integrated circuit of claim 7, wherein a plurality of the substantially flexible integrated circuits each comprises a layer of memory cells and adjacent to the layer of memory cells a low stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile.

26. The stacked integrated circuit of claim 7, wherein the at least one of the substantially flexible integrated circuits is made flexible by, in combination 1) thinning the monocrystalline semiconductor substrate to form a thinned surface, 2) polishing or smoothing the thinned surface, and 3) depositing over the monocrystalline semiconductor substrate one or more low stress silicon-based dielectric layers each having a stress of less than 5×

10⁸ dynes/cm² tensile.

27. The stacked integrated circuit of claim 7, wherein:

a first one of the substantially flexible integrated circuits comprises a logic circuit and others of the substantially flexible integrated circuits comprise memory circuits;

the logic circuit comprises first circuitry to retrieve data stored on the memory circuits via the interconnections and comprises second circuitry to perform ECC on the retrieved data.

28. The stacked integrated circuit of claim 27, wherein the retrieved data includes ECC syndrome bits used by the second circuitry to perform ECC on the retrieved data.

29. The stacked integrated circuit of claim 27, wherein the interconnections pass vertically through the logic circuit or the memory circuits.

30. The stacked integrated circuit of claim 7, wherein:

a first one of the substantially flexible integrated circuits comprises a logic circuit and others of the substantially flexible integrated circuits comprise memory circuits and one or more arrays of memory cells; and

the logic circuit comprises circuitry to reconfigure the memory circuits via the interconnections to avoid defects in the memory circuits.

31. The stacked integrated circuit of claim 30, wherein the logic circuit reconfigures access to the memory circuits by substituting redundant memory cells for defective memory cells in the memory circuits.

32. The stacked integrated circuit of claim 31, wherein the interconnections pass vertically through the logic circuit or the memory circuits.

33. The stacked integrated circuit of claim 7, wherein:

a first one of the substantially flexible integrated circuits comprises a logic circuit and others of the substantially flexible integrated circuits comprise memory circuits with DRAM memory cells;

the logic circuit comprises circuitry to refresh the DRAM memory cells via the interconnections.

34. The stacked integrated circuit memory of claim 33, wherein the interconnections pass vertically through the logic circuit or the memory circuits.

35. The stacked integrated circuit of claim 29, wherein the interconnections that pass vertically through the logic circuit or the memory circuits pass through the substantially flexible monocrystalline semiconductor substrate and each comprises a conductive center portion and an insulating portion surrounding the conductive center portion, wherein the insulating portion comprises a dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

36. The stacked integrated circuit of claim 32, wherein the interconnections that pass vertically through the logic circuit or the memory circuits pass through the substantially flexible monocrystalline semiconductor substrate and each comprises a conductive center portion and an insulating portion surrounding the conductive center portion, wherein the insulating portion comprises a dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

37. The stacked integrated circuit of claim 34, wherein the interconnections that pass vertically through the logic circuit or the memory circuits pass through the substantially flexible monocrystalline semiconductor substrate and each comprises a conductive center portion and an insulating portion surrounding the conductive center portion, wherein the insulating portion comprises a dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

38. The stacked integrated circuit of claim 28, wherein at least one of the logic circuit and the memory circuits comprises a plurality of vertical interconnections passing vertically therethrough, each of said vertical interconnections comprising a conductive center portion and an insulating portion surrounding the conductive center portion, wherein the insulating portion comprises a dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

39. The stacked integrated circuit of claim 31, wherein at least one of the logic circuit and the memory circuits comprises a plurality of vertical interconnections passing vertically therethrough, each of said vertical interconnections comprising a conductive center portion and an insulating portion surrounding the conductive center portion, wherein the insulating portion comprises a dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

40. The stacked integrated circuit of claim 33, wherein at least one of the logic circuit and the memory circuits comprises a plurality of vertical interconnections passing vertically therethrough, each of said vertical interconnections comprising a conductive center portion and an insulating portion surrounding the conductive center portion, wherein the insulating portion comprises a dielectric material having a stress of less than 5×

10⁸ dynes/cm² tensile.

41. The stacked integrated circuit of claim 1, wherein a process technology used to make at least one of the plurality of substantially flexible integrated circuits is different from a process technology used to make at least another one of the plurality of substantially flexible integrated circuits.

42. The stacked integrated circuit of claim 14, wherein a process technology used to make at least one of the plurality of substantially flexible integrated circuits is different from a process technology used to make at least another one of the plurality of substantially flexible integrated circuits.

43. The stacked integrated circuit structure of claim 1, wherein:

the plurality of substantially flexible integrated circuits form a stacked integrated circuit memory structure;

a majority of the stacked integrated circuit memory structure is partitioned into a plurality of block stacks, each block stack comprising at least one memory array controller block, a plurality of memory array blocks and an array of vertical interconnections that vertically interconnect the at least one memory array controller block and the plurality of memory array blocks and pass through at least one of the at least one memory array controller block and the plurality of memory array blocks, wherein the at least one memory array controller block comprises circuitry for performing memory accesses with the plurality of memory array blocks;

wherein at least two of the plurality of block stacks can independently and simultaneously perform memory accesses within the stacked integrated circuit memory structure, wherein said vertical interconnections comprise each array of vertical interconnections and the array of vertical interconnections of the at least two of the plurality of block stacks can independently and simultaneously transfer data during said memory accesses.

44. The stacked circuit structure of claim 43, wherein at least one block stack of the plurality of the block stacks comprises at least one memory array controller block comprising circuitry that performs error correction on read data from at least one of the memory array blocks of said at least one block stack, wherein read data is transferred through one or more vertical interconnections of the array of vertical interconnections of the at least one block stack.

45. The stacked circuit structure of claim 44, wherein the read data includes ECC data used by the circuitry of the at least one memory array controller block to perform error correction on the read data.

46. The stacked circuit structure of claim 43, wherein at least one block stack of the plurality of the block stacks comprises at least one memory array controller block comprising reconfiguration circuitry that performs reconfiguration of the array of vertical interconnections to avoid using one or more defective memory portions of the plurality of memory array blocks.

47. The stacked circuit structure of claim 46, wherein the reconfiguration circuitry substitutes for the one or more defective memory portions of the plurality of memory array blocks one or more redundant memory portions from at least one of the plurality of memory array blocks.

48. The stacked circuit structure of claim 47, wherein

the one or more defective memory portions comprise defective gate lines of the plurality of memory array blocks and the one or more redundant memory portions comprise redundant gate lines of the plurality of memory array blocks.

49. The stacked circuit structure of claim 43, wherein at least one block stack of the plurality of block stacks comprises at least one memory array controller block further comprising reconfiguration circuitry that performs reconfiguration of the array of vertical interconnections to avoid using one or more defective vertical interconnections of the at least one block stack.

50. The stacked circuit structure of claim 43, wherein at least one block stack of the plurality of block stacks comprises at least one memory array controller block further comprising refresh circuitry that performs refresh of one or more memory portions of the plurality of memory array blocks, wherein the refresh circuitry performs refresh of the one or more memory portions of the plurality of memory array blocks using one or more of the vertical interconnections of said at least one block stack.

51. The stacked circuit structure of claim 43, wherein at least one block stack of the plurality of block stacks comprises at least one memory array block controller further comprising test circuitry that performs testing of one or more memory portions of the plurality of memory array blocks, wherein the test circuitry tests the one or more memory portions of the plurality of memory array blocks using one or more of the vertical interconnections of said at least one block stack.

52. The stacked integrated circuit of claim 43, wherein the plurality of substantially flexible integrated circuits comprises a memory comprising at least one memory array and a memory controller, wherein at least one of:

the memory is reconfigurable by operation of the memory controller; and

the memory controller or one of the plurality of substantially flexible integrated circuit layers comprises circuitry for performing functional testing of the at least one memory array.

53. The apparatus of claim 1, further comprising a low-stress silicon-based dielectric layer formed above the substantially flexible monocrystalline semiconductor substrate and having a stress of less than 5×

10⁸ dynes/cm² tensile, wherein;

a backside of the substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing; and

at least one of the plurality of substantially flexible integrated circuits has edges that define its size in area; and

the substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges.

54. The apparatus of claim 1, further comprising a low-stress silicon-based dielectric layer formed above the substantially flexible monocrystalline semiconductor substrate and having a stress of less than 5×

10⁸ dynes/cm² tensile, wherein;

a backside of the substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing; and

at least one of the plurality of substantially flexible integrated circuits comprises a singulated die having a die area defined by its perimeter; and

the substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the die area.

55. The apparatus of claim 1, further comprising a low-stress silicon-based dielectric layer formed above the substantially flexible monocrystalline semiconductor substrate and having a stress of less than 5×

10⁸ dynes/cm² tensile, wherein;

a backside of the substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing; and

at least one of the plurality of substantially flexible integrated circuits is substantially flexible based on the substantially flexible monocrystalline semiconductor substrate being substantially flexible and the stress of the low stress silicon-based dielectric layer being less than 5×

10⁸ dynes/cm² tensile.

56. The stacked integrated circuit of claim 16, wherein a process technology used to make at least one of the substantially flexible integrated circuits is different from a process technology used to make at least another one of the plurality of substantially flexible integrated circuits.

57. The stacked integrated circuit of claim 43, wherein a process technology used to make at least one of the substantially flexible integrated circuits is different from a process technology used to make at least another one of the plurality of substantially flexible integrated circuits.

58. The stacked integrated circuit of claim 50, wherein a process technology used to make at least one of the substantially flexible integrated circuits is different from a process technology used to make at least another one of the plurality of substantially flexible integrated circuits.

59. The stacked integrated circuit of claim 53, wherein a process technology used to make at least one of the substantially flexible integrated circuits is different from a process technology used to make at least another one of the plurality of substantially flexible integrated circuits.

60. The stacked integrated circuit of claim 54, wherein a process technology used to make at least one of the substantially flexible integrated circuits is different from a process technology used to make at least another one of the plurality of substantially flexible integrated circuits.

61. The stacked integrated circuit of claim 55, wherein a process technology used to make at least one of the substantially flexible integrated circuits is different from a process technology used to make at least another one of the plurality of substantially flexible integrated circuits.

62. A stacked integrated circuit comprising:

a plurality of substantially flexible integrated circuits having topside and bottom-side surfaces, wherein said integrated circuits are in a stacked relation to one another, wherein at least one of the substantially flexible integrated circuits comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor water thinned by at least one of abrasion, etching and parting to expose a surface, and subsequently polishing or smoothing the exposed surface to form a polished or smoothed surface;

vertical interconnections that pass through one or more of the plurality of substantially flexible integrated circuits and electrically connect the plurality of substantially flexible integrated circuits; and

a low-stress silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm²;

wherein;

a process technology used to make a first integrated circuit of the plurality of substantially flexible integrated circuits is different from a process technology used to make a second integrated circuit of the plurality of substantially flexible integrated circuits;

the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing;

a first integrated circuit of the plurality of substantially flexible integrated circuits has edges that define its size in area, and the thinned, substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges; and

,

a second integrated circuit of the plurality of substantially flexible integrated circuits comprises an array of memory cells and is formed without a monocrystalline semiconductor substrate over the first integrated circuit of the plurality of substantially flexible integrated circuits and comprises at least one silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm².

63. The stacked integrated circuit of claim 62, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.

64. A stacked integrated circuit comprising:

a plurality of substantially flexible integrated circuits having topside and bottom-side surfaces, wherein said integrated circuits are in a stacked relation to one another, wherein at least one of the substantially flexible integrated circuits comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned by at least one of abrasion, etching and parting to expose a surface, and subsequently polishing or smoothing the exposed surface to form a polished or smoothed surface;

vertical interconnections that pass through one or more of the plurality of substantially flexible integrated circuits and electrically connect the plurality of substantially flexible integrated circuits; and

a low-stress silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm²;

wherein;

a process technology used to make a first integrated circuit of the plurality of substantially flexible integrated circuits is different from a process technology used to make a second integrated circuit of the plurality of substantially flexible integrated circuits;

the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing;

a first integrated circuit of the plurality of substantially flexible integrated circuits has edges that define its size in area, and the thinned, substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges;

a second integrated circuit of the plurality of substantially flexible integrated circuits comprises an array of non-volatile memory cells and is formed over the first integrated circuit of the plurality of substantially flexible integrated circuits and comprises at least one silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm²; and

,

the first integrated circuit of the plurality of substantially flexible integrated circuits comprising circuitry for storing a plurality of data bits per memory cell.

65. The stacked integrated circuit of claim 64, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.

66. A stacked integrated circuit comprising:

a plurality of substantially flexible integrated circuits having topside and bottom-side surfaces, wherein said integrated circuits are in a stacked relation to one another, wherein at least one of the substantially flexible integrated circuits comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned by at least one of abrasion, etching and parting to expose a surface, and subsequently polishing or smoothing the exposed surface to form a polished or smoothed surface;

vertical interconnections that pass through one or more of the plurality of substantially flexible integrated circuits and electrically connect the plurality of substantially flexible integrated circuits; and

a low-stress silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm²;

wherein;

a process technology used to make a first integrated circuit of the plurality of substantially flexible integrated circuits is different from a process technology used to make a second integrated circuit of the plurality of substantially flexible integrated circuits;

the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing;

a first integrated circuit of the plurality of substantially flexible integrated circuits has edges that define its size in area, and the thinned, substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges;

the stacked integrated circuit is substantially flexible based on a combination of one or more low-stress dielectric layers and the monocrystalline semiconductor substrate being substantially flexible;

a second integrated circuit of the plurality of substantially flexible integrated circuits comprises an array of non-volatile memory cells and is formed over the first integrated circuit of the plurality of substantially flexible integrated circuits and comprises at least one silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm²;

the first integrated circuit of the plurality of substantially flexible integrated circuits comprising circuitry for storing a plurality of data bits per memory cell; and

,

the first integrated circuit of the plurality of substantially flexible integrated circuits comprising error correction circuitry for detecting and correcting data read errors from the non-volatile memory cells of the second integrated circuit of the plurality of substantially flexible integrated circuits.

67. The stacked integrated circuit of claim 66, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.