Noise decoupling structure with through-substrate vias

• US 8,928,127 B2
• Filed: 09/24/2010
• Issued: 01/06/2015
• Est. Priority Date: 09/24/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chia-Chung, Jou, Chewn-Pu, Liu, Sally
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Kim, Sun M
• Application Number:
  US12/889,650
• Publication Number:
  US 20120074515A1
• Time in Patent Office: 1,565 Days
• Field of Search: 257/409, 257/508, 257/659, 257/665, 257/E29.009, 257/E29.012, 257/E29.013
• US Class Current: 257/659
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6666 for decoupling, e.g. bypass capacitors
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate.

Claims

1. A device comprising:

a substrate comprising a front surface and a back surface;

an integrated circuit device at the front surface of the substrate;

a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device;

a guard ring extending into the substrate and encircling the integrated circuit device, wherein the guard ring is formed of a conductive material;

a through substrate via (TSV) penetrating through the substrate and electrically coupled to the metal plate; and

an additional guard ring encircling the guard ring, the additional guard ring formed of an n-well region in the substrate;

wherein the TSV is laterally between the guard ring and the additional guard ring.

2. The device of claim 1, wherein the guard ring comprises a well region forming a well ring.

3. The device of claim 1 further comprising a deep well region directly underlying the integrated circuit device and electrically coupled to the guard ring.

4. The device of claim 3, wherein the TSV penetrates through the deep well region.

5. The device of claim 3 further comprising a shallow trench isolation (STI) region adjacent the integrated circuit device, wherein the TSV penetrates through the STI region.

6. The device of claim 1, wherein the TSV is outside the guard ring.

7. The device of claim 1, wherein the TSV is inside the guard ring, and is laterally between the integrated circuit device and the guard ring.

8. The device of claim 1, wherein the conductive material of the guard ring comprises an n-well region.

9. The device of claim 8, wherein the guard ring and the additional guard ring are disposed over a deep n-well region.

10. The device of claim 1, wherein the substrate has a semiconductor-on-insulator (SOI) structure.

11. A device comprising:

a semiconductor substrate comprising a front surface and a back surface;

an integrated circuit device at the front surface of the substrate;

a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device;

a first guard ring extending into the substrate and encircling the integrated circuit device, wherein the first guard ring is formed of a first well region;

a deep well region directly underlying the integrated circuit device and contacting the first guard ring, wherein the first guard ring and the deep well region are of a same conductivity type;

a through substrate via (TSV) penetrating through the substrate and the deep well region, and electrically coupled to the metal plate;

a second guard ring encircling the first guard ring, the second guard ring formed of an n-well region in the semiconductor substrate; and

a second well region directly over the deep well region, wherein the second well region is encircled by, and contacts, the first guard ring, and wherein the second well region and the deep well region are of opposite conductivity types.

12. The device of claim 11, wherein the first guard ring and the TSV are grounded.

13. The device of claim 11 further comprising a plurality of TSVs penetrating through the substrate and the deep well region and electrically coupled to the metal plate, wherein the plurality of TSVs and the TSV are distributed substantially uniformly surrounding the integrated circuit device.

14. The device of claim 11, wherein the TSV is laterally between the first and the second guard rings, wherein the TSV penetrates through a shallow trench isolation (STI) region disposed laterally between the first and the second guard rings, and wherein the STI region forms a ring encircling the first guard ring.

15. The device of claim 11, wherein the semiconductor substrate has a semiconductor-on-insulator (SOI) structure, with the TSV penetrating through the SOI structure.

16. A device comprising:

a p-type semiconductor substrate;

a deep n-well region in the semiconductor substrate;

a p-well region over and contacting the deep well region;

a guard ring formed of an n-well region in the p-type semiconductor substrate and encircling the p-well region, wherein the guard ring extends from a front surface of the p-type semiconductor substrate into the p-type semiconductor substrate, and wherein the guard ring contacts the deep n-well region;

a metal plate contacting a back surface of the semiconductor substrate;

a through substrate via (TSV) penetrating through the p-type semiconductor substrate and contacting the metal plate; and

an additional guard ring formed of an additional n-well region in the semiconductor substrate and encircling the guard ring, the additional guard ring extending from the front surface of the p-type semiconductor substrate into the p-type semiconductor substrate, and wherein the TSV is laterally between the guard ring and the additional guard ring.

17. The device of claim 16 further comprising an integrated circuit device comprising at least a portion in the p-well region and encircled by the guard ring, wherein the integrated circuit device is selected from the group consisting essentially of a metal-oxide-semiconductor (MOS) device, a MOS varactor, an inductor, and combinations thereof.

18. The device of claim 16, wherein the TSV penetrates through the deep n-well region.

19. The device of claim 16, wherein the TSV is inside the guard ring.

20. The device of claim 16, wherein the TSV is outside the guard ring, and wherein the deep well region overlaps an entirety of the p-well region and an entirety of the guard ring, and laterally extends beyond outer boundaries of the guard ring, and wherein the TSV penetrates through the deep n-well region.