Alignment marks in substrate having through-substrate via (TSV)

• US 8,928,159 B2
• Filed: 09/02/2010
• Issued: 01/06/2015
• Est. Priority Date: 09/02/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hsin, Tsai, Fang Wen, Lin, Jing-Cheng, Chiou, Wen-Chih, Jeng, Shin-Puu
• Primary Examiner(s): Clark, S. V.
• Assistant Examiner(s): SODERHOLM, KRISTA Z
• Application Number:
  US12/874,952
• Publication Number:
  US 20120056315A1
• Time in Patent Office: 1,587 Days
• Field of Search: 257/737, 257/E23.067, 257/E23.011, 257/E23.145, 257/E23.174, 257/774, 257/797
• US Class Current: 257/797
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

Claims

1. A device comprising:

a substrate comprising two major surfaces on opposite sides of the substrate, wherein the substrate is a semiconductor substrate, and wherein no active device is formed at either one of the two major surfaces of the substrate;

a first alignment mark comprising a first conductive through-substrate via (TSV) penetrating through the substrate and extending from the a first one of the two major surfaces to a second one of the two major surfaces; and

a dielectric layer on a backside of the substrate, wherein the first conductive TSV penetrates through the dielectric layer.

2. The device of claim 1, wherein the first alignment mark comprises a plurality of first conductive TSVs penetrating through the substrate.

3. The device of claim 2, wherein the plurality of first conductive TSVs are arranged in a rectangular region.

4. The device of claim 2, wherein the plurality of first conductive TSVs are aligned into two lines crossing each other.

5. The device of claim 1, further comprising a conductive feature over a backside of the substrate, wherein the conductive feature is not electrically coupled to the first conductive TSV.

6. The device of claim 1, wherein the first conductive TSV is electrically floating.

7. The device of claim 1, further comprising a second alignment mark on a front side of the substrate, wherein the second alignment mark includes a metal layer.

8. The device of claim 1, further comprising a second conductive TSV penetrating through the substrate and not electrically floating.

9. The device of claim 8, wherein the first conductive TSV and the second conductive TSV have substantially a same diameter.

10. The device of claim 8, wherein the first conductive TSV and the second conductive TSV have substantially a same height.

11. The device of claim 8, wherein the first conductive TSV and the second conductive TSV have substantially a same top-view shape.

12. The device of claim 8 further comprising a conductive feature on a backside of the substrate and electrically coupled to the second conductive TSV, wherein the conductive feature includes at least one of a redistribution line and a metal bump.

13. A method of forming a device, the method comprising:

forming a first and a second conductive through-substrate via (TSV) in a substrate;

performing a backside grinding on a backside of the substrate, wherein the first and the second conductive TSVs are exposed through a back surface of the substrate;

recessing the back surface of the substrate to make the first and the second conductive TSVs to protrude beyond the back surface;

forming a passivation layer on the back surface of the substrate;

removing portions of the passivation layers that overlap the first and the second conductive TSVs to expose the first and the second conductive TSVs; and

forming a conductive feature on a backside of the substrate and electrically coupled to the second conductive TSV by using the first conductive TSV as an alignment mark.

14. The method of claim 13, wherein the conductive feature comprises at least one of a redistribution line and a metal bump.

15. The method of claim 13, wherein the conductive feature is not electrically coupled to the first conductive TSV.

16. The method of claim 13, further comprising forming an additional alignment mark on a front side of the substrate.

17. The method of claim 13 further comprising forming an interconnect structure on a front side of the substrate, wherein the interconnect structure is not electrically coupled to the first conductive TSV.

18. The method of claim 13, wherein the forming the conductive feature comprises forming a redistribution line.

19. The method of claim 13, wherein the forming the conductive feature comprises forming a metal bump.

20. The method of claim 13, wherein the substrate further comprises a front surface opposite to the back surface, wherein a transistor is formed at the front surface of the substrate.