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Programming the behavior of individual chips or strata in a 3D stack of integrated circuits

  • US 8,928,350 B2
  • Filed: 09/07/2012
  • Issued: 01/06/2015
  • Est. Priority Date: 08/25/2011
  • Status: Active Grant
First Claim
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1. A strata manager within a 3D chip stack having two or more strata, the strata manager comprising:

  • a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata of the 3D chip stack for storing a set of bits,wherein the set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon.

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