Programming the behavior of individual chips or strata in a 3D stack of integrated circuits
First Claim
Patent Images
1. A strata manager within a 3D chip stack having two or more strata, the strata manager comprising:
- a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata of the 3D chip stack for storing a set of bits,wherein the set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon.
6 Assignments
0 Petitions
Accused Products
Abstract
There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.
58 Citations
23 Claims
-
1. A strata manager within a 3D chip stack having two or more strata, the strata manager comprising:
-
a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata of the 3D chip stack for storing a set of bits, wherein the set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. A stratum identifier within a 3D chip stack having two or more strata and multiple integrated circuits, the stratum identifier comprising:
-
a plurality of stratum identification circuits, each arranged on a respective one of the two or more strata, and each having “
N”
inter-stratum inputs and “
N”
inter-stratum outputs,wherein n is an integer equal to or greater than 1, and 2N is a number of the two or more strata, wherein the inter-stratum inputs from a respective one of the plurality of stratum identification circuits on each of the two or more strata are connected to and driven by the inter-stratum outputs from a different one of the plurality of stratum identification circuits on an adjacent one of the two or more strata, wherein inter-stratum input signals and inter-stratum output signals are provided as binary encoded values such that the inter-stratum output signals encode a value of the inter-stratum input signals incremented by 1, the inter-stratum output signals being available to at least some of the multiple integrated circuits on a same one of the two or more strata stratum so as to provide the encoded value therein as a unique binary pattern on each of the two or more strata. - View Dependent Claims (19, 20)
-
-
21. A stack-wide scan circuit within a 3D chip stack having two or more strata including a first terminal stratum and a second terminal stratum, the stack-wide scan circuit comprising:
-
a plurality of configurable scan chains, each including a scannable configuration register; an off-stack accessible input port connected in a broadcast configuration to each of the plurality of scan chains; an off-stack accessible output port on the first terminal stratum connected to a given one of the plurality of configurable scan chains on the first terminal stratum; and means for configuring the plurality of scan chains to selectively provide any of a plurality of different scan paths through the two or more strata. - View Dependent Claims (22, 23)
-
Specification