XY ternary content addressable memory (TCAM) cell and array

• US 8,929,115 B2
• Filed: 11/30/2011
• Issued: 01/06/2015
• Est. Priority Date: 11/30/2011
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Kohli, Nishu
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US13/307,167
• Publication Number:
  US 20130135914A1
• Time in Patent Office: 1,133 Days
• Field of Search: 365/49.1, 365/49.11, 365/49.15, 365/49.16, 365/49.17, 365/63, 365/72, 257/E21.661, 257/E27.098, 257/E27.099
• US Class Current: 365/49.1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.

Claims

1. A content addressable memory (CAM), comprising:

a plurality of CAM cells arranged in an array including columns and rows;

each CAM cell comprising a first SRAM cell, a second SRAM cell and a comparator circuit, the first and second SRAM cells having a horizontal topology layout with a longer side edge and a shorter side edge;

a plurality of match lines, each match line extending across the array and coupled to plural CAM cells, each match line oriented in a first direction that is parallel to the shorter side edge of the horizontal topology for the first and second SRAM cells in said plural CAM cells;

a plurality of bit lines, each bit line extending across the array and coupled to plural CAM cells, each bit line oriented in a second direction that is both perpendicular to the first direction and parallel to the longer side edge of the horizontal topology layout for the first and second SRAM cells in said plural CAM cells;

wherein the plurality of bit lines comprise;

a plurality of first bit lines, one first bit line per column or row of the array, each first bit line shared as a true bit line by the first and second SRAM cells in each CAM cell; and

a plurality of second bit lines, one second bit line per column or row of the array, wherein second bit lines are shared as a complement bit line by the first SRAM cell in one CAM cell and the second SRAM cell in a CAM cell in an adjoining column or row.

2. The CAM of claim 1, wherein the plurality of match lines extend across the array in the first direction along columns of the array.

3. The CAM of claim 2, further comprising a match line sensing circuit for each column of the array, each match line sensing circuit coupled to one of the plurality of match lines.

4. The CAM of claim 1, further comprising a plurality of first word lines, each first word extending across the array and coupled to first SRAM cells within plural CAM cells, each first word line oriented in the first direction that is parallel to the shorter side edge of the horizontal topology layout for the first and second SRAM cells in said plural CAM cells.

5. The CAM of claim 4, further comprising a plurality of second word lines, each second word extending across the array and coupled to second SRAM cells within plural CAM cells, each second word line oriented in the first direction that is parallel to the shorter side edge of the horizontal topology layout for the first and second SRAM cells in said plural CAM cells.

6. The CAM of claim 5, wherein the plurality of first and second word lines extend across the array in the first direction along columns of the array.

7. The CAM of claim 6, further comprising a wordline decoder circuit for each column of the array, each wordline decoder circuit coupled to one of the plurality of first word lines and one of the plurality of second word lines.

8. The CAM of claim 1, wherein the plurality of bit lines extend across the array in the first direction along rows of the array.

9. The CAM of claim 1, wherein the plurality of bit lines further comprise a plurality of third bit lines, one third bit line per row of the array, wherein third bit lines are shared as a complement bit line by the second SRAM cell in one CAM cell and the first SRAM cell in a CAM cell in an adjoining column or row.

10. The CAM of claim 9, further comprising, for each row:

a write driver;

a sense amplifier; and

a MUX circuit, said MUX circuit operable to selectively couple the write driver and sense amplifier to the first, second and third bit lines of each row.

11. The CAM of claim 1, wherein the plurality of CAM cells comprise a plurality of ternary CAM cells.

12. A content addressable memory (CAM), comprising:

a plurality of CAM cells arranged in an array including a plurality of rows and a plurality of columns; and

a plurality of word line decoders, wherein each wordline decoder is coupled to a particular column;

wherein each CAM cell comprises a first SRAM cell, a second SRAM cell and a comparator circuit;

wherein each SRAM cell has a horizontal topology layout with a rectangular perimeter defined by a longer side edge and a shorter side edge; and

wherein the longer side edge is oriented parallel to the rows of the array and the shorter side edge is oriented parallel to the columns of the array;

a plurality of bit lines, each bit line extending across the array and coupled to plural CAM cells, each bit line oriented parallel to rows of the array;

wherein the plurality of bit lines comprise;

a plurality of first bit lines, one first bit line per row of the array, each first bit line shared as a true bit line by the first and second SRAM cells in each CAM cell; and

a plurality of second bit lines, one second bit line per row of the array, each second bit line except for a first one of the second bit lines, shared as a complement bit line by the first SRAM cell in one CAM cell and the second SRAM cell in an adjacent CAM cell along the column.

13. The CAM of claim 12, further comprising:

a plurality of match lines, each match line extending across the array and coupled to plural CAM cells, each match line oriented parallel to the columns of the array.

14. The CAM of claim 12, further comprising a plurality of first word lines coupled to the wordline decoder, each first word line extending across the array and coupled to first SRAM cells within plural CAM cells, each first word line oriented parallel to the columns of the array.

15. The CAM of claim 14, further comprising a plurality of second word lines coupled to the wordline decoder, each second word extending across the array and coupled to second SRAM cells within plural CAM cells, each second word line oriented parallel to the columns of the array.

16. The CAM of claim 12, wherein the plurality of bit lines further comprise a plurality of third bit lines, one third bit line per row of the array, each third bit line except for a last one of the third bit lines, shared as a complement bit line by the second SRAM cell in one CAM cell and the first SRAM cell in an adjacent CAM cell along the column.

17. The CAM of claim 16, further comprising, for each row:

a write driver;

a search data driver;

a sense amplifier; and

a MUX circuit, said MUX circuit operable to selectively couple the write driver and sense amplifier to the first, second and third bit lines of each row.

18. A content addressable memory (CAM) cell for a memory array having rows and columns, comprising:

a first SRAM cell;

a second SRAM cell;

a comparator circuit coupled to the first and second SRAM cells;

wherein the first and second SRAM cells having a horizontal topology layout with a longer side edge and a shorter side edge;

a match line coupled to an output of the comparator circuit, said match line oriented in a column direction that is parallel to the shorter side edge of the horizontal topology for the first and second SRAM cells;

a first bit line coupled to true storage nodes of the first and second SRAM cells, said first bit line oriented in a row direction that is both perpendicular to the column direction and parallel to the longer side edge of the horizontal topology layout for the first and second SRAM cells;

a second bit line coupled to a complement storage node of the first SRAM cell, said second bit line also oriented in the row direction and configured to be shared with another CAM cell in an adjacent row; and

a third bit line coupled to a complement storage node of the second SRAM cell, said third bit line also oriented in the row direction and configured to be shared with yet another CAM cell in an another adjacent row.

19. The CAM cell of claim 18, wherein the second and third bit lines are each positioned along a boundary between adjacent CAM cells in adjacent rows.

20. The CAM cell of claim 19, wherein the first bit line is positioned between the second third bit lines.

21. The CAM cell of claim 19, further comprising a search line coupled to an input of the comparator circuit, said search line also oriented in the row direction and positioned between the second third bit lines.