Layout of memory cells
First Claim
Patent Images
1. A semiconductor structure comprising:
- a first strap cell having a first strap cell reference voltage (VSS) region;
a first read port having a first read port VSS region, a first read port read bit line region, and a first read port poly region; and
a first VSS terminal configured to electrically couple the first strap cell VSS region and the first read port VSS region.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
-
Citations
20 Claims
-
1. A semiconductor structure comprising:
-
a first strap cell having a first strap cell reference voltage (VSS) region; a first read port having a first read port VSS region, a first read port read bit line region, and a first read port poly region; and a first VSS terminal configured to electrically couple the first strap cell VSS region and the first read port VSS region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A structure comprising:
-
a first segment including a first strap cell; and a plurality of first read ports; and a second segment including a second strap cell; and a plurality of second read ports, wherein a first strap cell reference voltage (VSS) region of the first strap cell and a first read port VSS region of a first read port belonging to the plurality of first read ports are electrically coupled together through a first VSS contact terminal; a second strap cell VSS region of the second strap cell and a second read port VSS region of a second read port belonging to the plurality of second read ports are electrically coupled together through a second VSS contact terminal; and a third read port VSS region of a third read port belonging to the plurality of first read ports and a fourth read port VSS region of a fourth read port belonging to the plurality of second read ports are electrically coupled together through a third VSS contact terminal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
-
-
17. A method comprising:
-
configuring a first reference voltage (VSS) contact terminal to couple a first strap cell VSS region of a first strap cell and a first read port VSS region of a first read port; configuring a first read bit line contact terminal to couple a first read bit line region of the first read port to a first read bit line; configuring a second VSS contact terminal to couple a second strap cell VSS region of a second strap cell and a second read port VSS region of a second read port; and configuring a second read bit line contact terminal to couple a second read bit line region of the second read port to a second read bit line different from the first read bit line. - View Dependent Claims (18, 19, 20)
-
Specification