Selecting a master processor from an ambiguous peer group

• US 8,929,251 B2
• Filed: 01/08/2013
• Issued: 01/06/2015
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Engebretsen, David R., Knight, Stephen A., Lange-Pearson, Adam C., Saley, Jaimeson J.
• Primary Examiner(s): Mered, Habte
• Application Number:
  US13/736,413
• Publication Number:
  US 20130155837A1
• Time in Patent Office: 728 Days
• Field of Search: 709208-209, 709/223, 709211-216, 370/254, 370/255, 370/258, 370/389, 370/392, 370/216, 370/218, 710/105, 710/305, 710/22, 710/110, 700/2, 700/3, 700/5
• US Class Current: 370/254
• CPC Class Codes: H04L 41/0803 Configuration setting
• CPC Class Codes: H04L 41/12 Discovery or management of network topologies
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 67/1051 Group master selection mechanisms

Abstract

A distributed switch may include a plurality of special-purpose processors that control the different functions of the switch. To enable some special services, however, the distributed switch may need one of these processors to perform the role of a master. When a processor is powered on, the processor may publish a corresponding unique ID. Before electing the master, the special-purpose processors may use a discovery process to identify the network topology of the switch and evaluate the published IDs to determine which processor should be the master. If all the processors nominate the same master processor, then that processor is elected as the master and may finish configuring the distributed switch to enable the special services.

Claims

1. A method of electing a master processor from a plurality of processors, comprising:

storing in a first portion of a shared memory a first unique identifier for a first processor of the plurality of processors, wherein the shared memory is accessible by the plurality of processers via a network fabric;

traversing the network fabric comprising the plurality of processors to identify a network topology, while traversing the network fabric to identify the network topology;

reading, from a second portion of the shared memory, a second unique identifier for a second processor of the plurality of processors,

determining, based on one or more criteria, a nominee identifier from among the first and the second unique identifiers, and

storing the nominee identifier in a register in the first portion of the shared memory, wherein the nominee identifier is read from the register by one of the plurality of processors; and

electing the master processor that corresponds to the nominee identifier.

2. The method of claim 1, wherein electing the master processor that corresponds to the nominee identifier further comprises:

after storing the nominee identifier in the register, determining whether the second portion of the shared memory contains the same nominee identifier;

if so, electing the master processor that corresponds to the same nominee identifier; and

otherwise, determining whether a different unique identifier stored in the second portion of the shared memory better satisfies the one or more criteria than the nominee identifier.

3. The method of claim 2, further comprising, if the different unique identifier better satisfies the one or more criteria than the nominee identifier:

re-traversing the network fabric to identify a third processor of the plurality of processors, wherein the third processor stores a third unique identifier in a third portion of the shared memory; and

determining, based on the one or more criteria, a different nominee identifier from among the first, the second, and the third unique identifiers.

4. The method of claim 1, wherein the first and the second portions of the shared memory are distributed such that each portion is uniquely located on separate hardware components.

5. The method of claim 4, wherein at least two of the plurality of processors are located on separate hardware components.

6. The method of claim 4, wherein the first portion of the shared memory and the first processor are both located on one of the separate hardware components, wherein, before the master processor is elected, only the first processor is permitted to write data to the first portion of the shared memory.

7. The method of claim 1, further comprising:

upon determining that the elected master processor fails, electing a new master processor.

8. The method of claim 1, wherein the first portion of the shared memory is disposed on a sub-switch associated with the first processor, and the second portion of the shared memory is disposed on a sub-switch associated with the second processor.

9. The method of claim 1, wherein each processor of the plurality of processors nominates a respective processor of the plurality of processors as the master processor.

10. The method of claim 1, wherein the traversing the network fabric comprises crawling through a switching layer to locate each sub-switch of different switch modules.

11. The method of claim 10, wherein the traversing the network fabric comprises crawling along direct connections between bridging elements of each of the sub-switches of the different switch modules.

12. A method, comprising:

providing a plurality of switch modules, and each of the plurality of switch modules including a respective processor of a plurality of processors, each of the respective processors including a respective unique identifier;

storing the unique identifiers in respective registers of the plurality of switch modules, wherein the registers are accessible by any of the plurality of processers via a network fabric;

traversing the network fabric with each of the plurality of processors to identify a network topology by identifying the plurality of switch modules;

nominating a candidate master processor at each of the plurality of processors by reading with each of the plurality of processors the unique identifiers stored within the registers of the plurality of switch modules when traversing the network fabric; and

electing a master processor based on a consensus of the candidate master processors.

13. The method of claim 12, wherein the traversing the network fabric comprises identifying sub-switches of the plurality of switch modules.

14. The method of claim 12, wherein the traversing the network fabric comprises crawling along direct connections between bridging elements of each of the sub-switches of the plurality of switch modules.