Random number generation circuit

• US 8,930,428 B2
• Filed: 03/23/2012
• Issued: 01/06/2015
• Est. Priority Date: 09/29/2009
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yasuda, Shinichi, Ikegami, Kazutaka
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US13/428,150
• Publication Number:
  US 20120221616A1
• Time in Patent Office: 1,019 Days
• Field of Search: 708/250, 708/251, 708/255
• US Class Current: 708/251
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

According to one embodiment, a random number generation circuit includes an oscillation circuit and a holding circuit. The oscillation circuit has an amplifier array and a high-noise circuit. Amplifiers are connected in series in the amplifier array, and the amplifier array has a terminal between neighboring amplifiers. The high-noise circuit is inserted between other neighboring amplifiers in the amplifier array, and the high-noise circuit generates noise required to generate jitter in an oscillation signal from the amplifier array. The holding circuit outputs, as a random number, the oscillation signal held according to a clock signal.

Claims

1. A random number generation circuit comprising:

an oscillation circuit which has an amplifier array in which a plurality of amplifiers are connected in series, and which has a terminal between neighboring amplifiers, and a high-noise circuit which is inserted between other neighboring amplifiers in the amplifier array, and generates noise required to generate jitter in an oscillation signal from the amplifier array; and

a holding circuit which is connected to the terminal, holds the oscillation signal according to a clock signal having a frequency lower than an oscillation frequency of the oscillation signal, and outputs, as a random number, the oscillation signal held according to the clock signal, wherein the high-noise circuit comprises;

an NMOS transistor which has a first gate terminal, a first source terminal, and a first drain terminal, and in which the first drain terminal is connected to a high-potential side power supply and; and

a PMOS transistor which has a second gate terminal, a second source terminal, and a second drain terminal, and in which the second drain terminal is connected to the low-potential side power supply, the second gate terminal is connected to the first gate terminal, and the second source terminal is connected to the first source terminal.

2. The circuit according to claim 1, wherein the NMOS transistor further has a first substrate terminal connected to the low-potential side power supply, and the PMOS transistor further has a second substrate terminal connected to the high-potential side power supply.

3. The circuit according to claim 1, wherein the amplifiers are CMOS inverters.

4. The circuit according to claim 1, wherein at least one of the amplifiers comprises a control terminal used to control a delay of the oscillation signal according to a control voltage.

5. A random number generation circuit comprising:

an oscillation circuit which has an amplifier array in which a plurality of amplifiers are connected in series, and which has a terminal between neighboring amplifiers, and a high-noise circuit which is inserted between other neighboring amplifiers in the amplifier array, and generates noise required to generate jitter in an oscillation signal from the amplifier array; and

a holding circuit which is connected to the terminal, holds the oscillation signal according to a clock signal having a frequency lower than an oscillation frequency of the oscillation signal, and outputs, as a random number, the oscillation signal held according to the clock signal, wherein the holding circuit comprises;

a first holding circuit which holds and outputs the oscillation signal according to a first clock having a frequency lower than the oscillation frequency of the oscillation signal;

an XOR gate which is connected to an output of the first holding circuit;

a second holding circuit which is connected to an output of the XOR gate, holds the output from the XOR gate according to a second clock having a frequency lower than the oscillation frequency of the oscillation signal, and outputs the held output as a random number; and

a third holding circuit which is connected to the output of the XOR gate, and holds and outputs the output from the XOR gate according to the first clock; and

an OR gate which computes and outputs a logical sum of an output from the third holding circuit and a reset, and the XOR gate computes an exclusive OR operation of an output from the OR gate and the output from the first holding circuit.

6. The circuit according to claim 5, further comprising a check circuit which is connected to the output of the first holding circuit, and outputs an error signal.