Multiple class memory systems

• US 8,930,647 B1
• Filed: 04/06/2012
• Issued: 01/06/2015
• Est. Priority Date: 04/06/2011
• Status: Active Grant

• Current Assignee: P4tents1 LLC
• Original Assignee: P4tents1 LLC
• Inventors: Smith, Michael S
• Primary Examiner(s): Cardwell, Eric S
• Application Number:
  US13/441,132
• Time in Patent Office: 1,005 Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0824 Distributed directories, e.g. linked lists of caches
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 2206/1014 One time programmable [OTP] memory, e.g. PROM, WORM
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 9/44557 Code layout in executable memory
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/4824 : Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus is provided comprising a physical memory sub-system including a first memory of a first memory class and a second memory of a second memory class, the second memory being communicatively coupled to the first memory. The apparatus is configured such that the first memory and the second memory are capable of receiving instructions via the memory bus. A system and method are also provided for circuit cooperation. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit. Furthermore, the system is operable such that the at least one first circuit and the at least one additional circuit cooperate to carry out at least one task.

Claims

1. An apparatus, comprising:

a physical memory sub-system including;

a first memory of a first memory class; and

a second memory of a second memory class, the second memory communicatively coupled to the first memory;

wherein the apparatus is configured such that the first memory and the second memory are capable of being used for a random access data read from the first memory via the second memory as a result of the physical memory sub-system receiving multiple instructions via a single memory bus, by;

receiving an instruction via the single memory bus for operating on data, that results in;

a first operation on at least a portion of the data in connection with the first memory,

a second operation in connection with the second memory, that results in storage of the at least portion of the data in the second memory, and

a status being provided; and

after the status being provided, receiving another instruction via the single memory bus for operating on the at least portion of the data, that results in the at least portion of the data being read from the second memory;

wherein the apparatus is configured such that the physical memory sub-system requires receipt of the multiple instructions via the single memory bus for the random access data read from the first memory via the second memory.

2. The apparatus of claim 1, wherein the first memory class includes non-volatile memory, and the second memory class includes volatile memory.

3. The apparatus of claim 1, wherein the communicative coupling includes a connection via a buffer device.

4. The apparatus of claim 1, wherein the first memory class includes flash memory, and the second memory class includes dynamic random access memory.

5. The apparatus of claim 1, wherein the apparatus is configured such that the second memory of the second memory class is capable of serving as at least one of a temporary store or a de-staging mechanism for the first memory of the first memory class.

6. The apparatus of claim 1, wherein the apparatus is configured such that the second memory of the second memory class is capable of serving as a buffer.

7. The apparatus of claim 1, wherein the apparatus is configured such that the single memory bus is associated with a DDR3 or DDR4 protocol.

8. The apparatus of claim 7, wherein the apparatus is configured such that commands associated with another protocol are received via the single memory bus utilizing the DDR3 or DDR4 protocol.

9. The apparatus of claim 7, wherein the apparatus is configured such that commands associated with a SATA protocol are received via the single memory bus utilizing the DDR3 or DDR4 protocol.

10. The apparatus of claim 1, wherein the first memory includes NAND flash memory and the second memory includes dynamic random access memory, and the physical memory sub-system further includes:

a first buffer including the second memory, the first buffer capable of being communicatively coupled to the single memory bus; and

a second buffer communicatively coupled to a third memory, the second buffer communicatively coupled between the first buffer and the first memory such that the second buffer is communicatively coupled to the first buffer via a first additional memory bus and the second buffer is communicatively coupled to the first memory via a second additional memory bus.

11. The apparatus of claim 10, wherein the apparatus is configured such that the second memory includes dynamic random access memory that is embedded dynamic random access memory.

12. The apparatus of claim 10, wherein the apparatus is configured such that the third memory is of the second memory class.

13. The apparatus of claim 10, wherein the apparatus is configured such that the third memory is of a third memory class.

14. The apparatus of claim 10, wherein the apparatus is configured such that the second buffer includes the third memory.

15. The apparatus of claim 10, wherein the apparatus is configured such that the second memory of the first buffer is capable of serving as at least one of a temporary store or a de-staging mechanism for the first memory.

16. The apparatus of claim 10, wherein the apparatus is configured such that at least two of the first memory, the second memory, and the third memory are hierarchically coupled.

17. The apparatus of claim 10, wherein the apparatus is configured such that the single memory bus is associated with a DDR3 or DDR4 protocol.

18. The apparatus of claim 10, wherein the apparatus is configured such that the first additional memory bus is associated with a SATA protocol.

19. The apparatus of claim 10, wherein the apparatus is configured such that the second additional memory bus is associated with a NAND flash protocol.

20. The apparatus of claim 1, wherein the physical memory sub-system includes:

NAND flash memory;

dynamic random access memory;

a first circuit for receiving DDR signals and converting the DDR signals to SATA signals, the first circuit including embedded dynamic random access memory; and

a second circuit for receiving the SATA signals and converting the SATA signals to NAND flash signals, the second circuit communicatively coupled to the first circuit via a first additional memory bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a second additional memory bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the dynamic random access memory.

21. The apparatus of claim 20, wherein the apparatus is configured such that the first circuit is capable of being communicatively coupled to the single memory bus which is associated with a DDR protocol, the NAND flash memory is the first memory, and the embedded dynamic access memory is the second memory.

22. The apparatus of claim 20, wherein the apparatus is configured such that the second circuit includes the dynamic random access memory.

23. The apparatus of claim 20, wherein the apparatus is configured for, in connection with one or more of the multiple instructions, translating a first protocol associated with the single memory bus into a second protocol associated with at least one of the first additional memory bus or the second additional memory bus.

24. The apparatus of claim 20, wherein the apparatus is configured for emulating an appearance that only a single memory class is present.

25. The apparatus of claim 20, wherein the apparatus is configured for emulating an appearance that a different memory class is present.

26. The apparatus of claim 20, wherein the apparatus is configured such that at least one of the first circuit or the second circuit provides compatibility between two signals.

27. The apparatus of claim 1, wherein the apparatus is configured for executing a plurality of threads in connection with the first memory, and fetching one or more pages from the second memory using a time between the execution of the plurality of threads.

28. The apparatus of claim 27, wherein the apparatus is configured such that the fetching the one or more pages includes moving particular data between the first memory and the second memory.

29. The apparatus of claim 27, wherein the apparatus is configured such that the fetching the one or more pages includes transferring particular data between the first memory and the second memory.

30. The apparatus of claim 27, wherein the apparatus is configured such that the fetching the one or more pages includes retrieving particular data.

31. The apparatus of claim 27, wherein the apparatus is configured such that the fetching the one or more pages includes issuing a command.

32. The apparatus of claim 27, wherein the apparatus is configured such that the fetching of pages is performed in hardware and software.

33. The apparatus of claim 27, wherein the apparatus is configured such that the executing of at least one of the plurality of threads in connection with the first memory, involves the first operation and the second operation.

34. The apparatus of claim 1, wherein the apparatus further includes a third memory, and the third memory is communicatively coupled to the second memory.

35. The apparatus of claim 34, wherein the first memory class includes flash memory, the second memory class includes dynamic random access memory.

36. The apparatus of claim 1, wherein the apparatus further includes a third memory, the third memory communicatively coupled to at least one of the first memory or the second memory.

37. The apparatus of claim 36, wherein the apparatus is configured such that the third memory is of a third memory class.

38. The apparatus of claim 36, wherein the apparatus is configured such that the first memory includes NAND flash memory, the second memory includes embedded dynamic random access memory for serving as at least one of a temporary store or a de-staging mechanism, and the third memory includes dynamic random access memory for serving as a buffer.

39. The apparatus of claim 36, wherein the apparatus is configured such that receiving at least one of the multiple instructions via the single memory bus, results in a third operation on at least a portion of the data in connection with the third memory.

40. The apparatus of claim 1, wherein the apparatus is configured for receiving a first read command in connection with particular data, and issuing a second read command in connection with the particular data in response to the first read command.

41. The apparatus of claim 40, wherein the apparatus is configured such that the first read command is standard and is capable of being received from an operating system by a driver utilizing a first speed;

and the second read command is non-standard and is issued by the driver to the physical memory sub-system utilizing a second speed via the single memory bus.

42. The apparatus of claim 1, and further comprising the single memory bus.

43. The apparatus of claim 42, wherein the single memory bus includes at least two of a command bus, an address bus, a data bus, and a control bus.

44. The apparatus of claim 42, wherein the single memory bus includes a command or control bus;

an address bus; and

a data bus.

45. The apparatus of claim 1, wherein the apparatus is configured such that the instruction is of a same type as the another instruction.

46. The apparatus of claim 1, wherein the apparatus is configured such that the instruction is of a different type from the another instruction.

47. The apparatus of claim 1, wherein at least one additional memory bus is included via which at least one of the first memory or the second memory is incapable of receiving the multiple instructions.

48. The apparatus of claim 1, wherein the apparatus is configured such that the first operation includes a read operation.

49. The apparatus of claim 1, wherein the apparatus is configured such that the second operation includes a copy or transfer operation.

50. The apparatus of claim 1, wherein the apparatus is configured such that the at least portion of the data includes an entirety of the data.

51. The apparatus of claim 1, wherein the apparatus is configured such that the data includes a page.

52. The apparatus of claim 1, wherein the apparatus is configured such that the data includes a single portion of a page.

53. The apparatus of claim 1, wherein the apparatus is configured such that the status indicates that the at least portion of the data is stored in the second memory.

54. The apparatus of claim 1, wherein the apparatus is configured such that the instruction is a standard instruction that results in at least one non-standard instruction that:

results in the first operation that includes a read operation for reading the at least portion of the data from the first memory, and further results in the second operation that is for placing the at least portion of the data in the second memory.

55. The apparatus of claim 54, wherein the apparatus is configured such that the non-standard instruction includes a Cache Miss instruction.

56. The apparatus of claim 54, wherein the apparatus is configured such that the non-standard instruction includes a special instruction.

57. The apparatus of claim 54, wherein the apparatus is configured such that the non-standard instruction includes special data.

58. The apparatus of claim 54, wherein the apparatus is configured such the physical memory sub-system requires the multiple instructions because the apparatus is configured for emulating an appearance that a different memory class is present.

59. The apparatus of claim 54, wherein the apparatus is configured such the physical memory sub-system requires the multiple instructions because the apparatus is configured for emulating an appearance that only a single memory class is present.

60. The apparatus of claim 1, wherein the apparatus is configured such that the first memory and the second memory are hierarchically coupled.

61. A system comprising the apparatus of claim 1, and further comprising a computer program product including code for cooperating with the apparatus such that the first memory and the second memory are capable of receiving the multiple instructions via the single memory bus.

62. A system comprising the apparatus of claim 1, and further comprising a central processing unit for cooperating with the apparatus such that the first memory and the second memory are capable of receiving the multiple instructions via the single memory bus.

63. The apparatus of claim 1, wherein the apparatus is configured such that at least one of the multiple instructions includes at least one of a copy command, a read command, or a write command.

64. The apparatus of claim 1, wherein the apparatus is configured such that the random access data read is performed on the fly.

65. The apparatus of claim 1, wherein the apparatus is configured such that the random access data read is one of a plurality of random access reads interspersed with a plurality of random access writes performed in real-time.

66. The apparatus of claim 1, wherein the apparatus is configured such that the random access data read is performed for non-backup purposes.

67. The apparatus of claim 1, wherein the apparatus is configured such that the random access includes an arbitrary access.

68. The apparatus of claim 1, wherein the apparatus is configured such that the random access includes an access in connection with at least one of an arbitrary time or an arbitrary address.

69. The apparatus of claim 1, wherein the apparatus is configured such that the random access includes a burst random access.

70. The apparatus of claim 1, wherein the apparatus is configured such that a SATA bus is communicatively coupled between the first memory and the second memory.

71. The apparatus of claim 1, wherein the apparatus is configured such that the status includes a status message.

72. The apparatus of claim 1, wherein the apparatus is configured such that the status is provided by being made accessible to a source of the multiple instructions.

73. The apparatus of claim 1, wherein the apparatus is configured such that the status is provided by being made accessible to a central processing unit from which the multiple instructions are received.

74. The apparatus of claim 1, wherein the apparatus is configured such that the multiple instructions are received via the single memory bus, and other instructions are communicated via another memory bus.

75. The apparatus of claim 1, wherein the apparatus is configured such that the multiple instructions include the instruction, the another instruction, and yet another instruction.

76. The apparatus of claim 1, wherein the apparatus is configured such that the instruction and the another instruction each include read instructions.

77. The apparatus of claim 1, wherein the apparatus is configured such that at least one of the first operation, the second operation, or the status results from receiving the instruction, utilizing at least one additional instruction.

78. The apparatus of claim 1, wherein the apparatus is configured such that at least one additional operation exists between at least two of the first operation, the second operation, and the status.

79. The apparatus of claim 1, wherein the apparatus is configured such that the first operation occurs before the second operation, and the second operation occurs before the status being provided.