Master core discovering enabled cores in microprocessor comprising plural multi-core dies

• US 8,930,676 B2
• Filed: 11/17/2011
• Issued: 01/06/2015
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Darius D.
• Primary Examiner(s): KIM, KENNETH S
• Application Number:
  US13/299,207
• Publication Number:
  US 20120166763A1
• Time in Patent Office: 1,146 Days
• Field of Search: None
• US Class Current: 712/32
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

A core configuration discovery method and corresponding microprocessor are provided that does not rely on off-core logic or queries by system BIOS. Reset microcode is provided in the microprocessor'"'"'s cores. Upon reset, the microcode queries and/or receives from other cores configuration-revealing information and collects the configuration-revealing information to determine a composite core configuration for the microprocessor. The composite core configuration may reveal the number of enabled cores, identify the enabled cores, reveal a hierarchical coordination system of the multi-core processor, such as a nodal map of the cores for certain inter-core communication processes or restricted activities, identify various domains and domain masters within such a system, and/or identify resources, such as voltage sources, clock sources, and caches, shared by various domains of the microprocessor. The composite core configuration may be used for power state management, reconfiguration, and other purposes.

Claims

1. A microprocessor configured to communicate with system memory over a system bus, the microprocessor comprising:

a plurality of semiconductor dies, wherein each of the dies comprises a plurality of processing cores, wherein one of the plurality of processing cores of each of the dies is designated as the master core, wherein each of the master cores is configured to;

communicate with each of the other cores of its die over inter-core communication channels to determine the number of enabled cores of the die, in response to a reset of the microprocessor, and

communicate with the master core of each of the other dies over inter-die communication channels to determine the number of enabled cores of the microprocessor, after determining the number of enabled cores of the die;

wherein the inter-core and inter-die communication channels are external to the system bus.

2. The microprocessor of claim 1, wherein each of the master cores is further configured to:

use the determined number of enabled cores of the microprocessor during operation of the microprocessor.

3. The microprocessor of claim 2, wherein each of the master cores is configured to use the determined number of enabled cores of the microprocessor during operation of the microprocessor by providing the determined number of enabled cores of the microprocessor as a result value in response to execution of a user program instruction that requests the number of cores of the microprocessor.

4. The microprocessor of claim 3, wherein each of the master cores is configured to use the determined number of enabled cores of the microprocessor during operation of the microprocessor by performing power management of the multi-core microprocessor based of the determined number of enabled cores of the microprocessor.

5. The microprocessor of claim 4, wherein each of the master cores is configured to perform power management of the multi-core die based on the determined number of enabled cores of the microprocessor by synchronizing power state changes by the cores.

6. The microprocessor of claim 4, wherein each of the master cores is configured to perform power management of the multi-core die based on the determined number of enabled cores of the microprocessor by managing a shared voltage source.

7. The microprocessor of claim 4, wherein each of the master cores is configured to perform power management of the multi-core die based on the determined number of enabled cores of the microprocessor by managing a shared clock source.

8. The microprocessor of claim 1, wherein each of the master cores is configured to communicate with each of the other cores of its die to determine the number of enabled cores of the die by determining that one of the other cores of the die is not enabled if the one of the other cores of the die does not respond to a message from the master core within a predetermined amount of time.

9. The microprocessor of claim 1, wherein each of the master cores is configured to communicate with the master core of each of the other dies to determine the number of enabled cores of the microprocessor by:

sending a message to the master core of each of the other dies that specifies the determined number of enabled cores of the die; and

receiving a message from the master core of each of the other dies that specifies the determined number of enabled cores of the other die.

10. The microprocessor of claim 9, wherein each of the master cores is configured to communicate with the master core of each of the other dies to determine the number of enabled cores of the microprocessor by determining that one of the other master cores is not enabled if the one of the other master cores does not respond to the message from the master core within a predetermined amount of time.

11. The microprocessor of claim 1, wherein each of the dies includes inter-core communication wires that provide the inter-core communication channels used by the master core to communicate with each of the other cores of its die to determine the number of enabled cores of the die, wherein the multi-core microprocessor also includes inter-die communication wires that provide the inter-die communication channels used by the master cores to communicate with the master core of each of the other dies to determine the number of enabled cores of the microprocessor.

12. The microprocessor of claim 1, wherein microcode of the master core of each die is configured to communicate with each of the other cores of its die to determine the number of enabled cores of the die and to communicate with the master core of each of the other dies to determine the number of enabled cores of the microprocessor.

13. A method for dynamically determining the configuration of a multi-core microprocessor configured to communicate with system memory over a system bus comprising multiple semiconductor dies each comprising multiple processing cores, the method comprising:

communicating over inter-core communication channels with, by a master core of each of the dies, each of the other cores of the die to determine the number of enabled cores of the die, in response to a reset of the microprocessor; and

communicating over inter-die communication channels with, by the master core of each of the dies, the master core of each of the other dies to determine the number of enabled cores of the microprocessor, after determining the number of enabled cores of the die;

wherein the inter-core and inter-die communication channels are external to the system bus.

14. The method of claim 13, further comprising:

using the determined number of enabled cores of the microprocessor during operation of the microprocessor.

15. The method of claim 14, wherein said using the determined number of enabled cores of the microprocessor during operation of the microprocessor comprises providing the determined number of enabled cores of the microprocessor as a result value in response to execution of a user program instruction that requests the number of cores of the microprocessor.

16. The method of claim 15, wherein said using the determined number of enabled cores of the microprocessor during operation of the microprocessor comprises performing power management of the multi-core microprocessor based of the determined number of enabled cores of the microprocessor.

17. The method of claim 16, wherein said performing power management of the multi-core die based on the determined number of enabled cores of the microprocessor comprises synchronizing power state changes by the cores.

18. The method of claim 16, wherein said performing power management of the multi-core die based on the determined number of enabled cores of the microprocessor comprises management of a shared voltage source.

19. The method of claim 16, wherein said performing power management of the multi-core die based on the determined number of enabled cores of the microprocessor comprises management of a shared clock source.

20. The method of claim 13, wherein said communicating with each of the other cores of the die to determine the number of enabled cores of the die comprises determining that one of the other cores of the die is not enabled if the one of the other cores of the die does not respond to a message from the master core within a predetermined amount of time.

21. The method of claim 13, wherein said communicating with the master core of each of the other dies to determine the number of enabled cores comprises:

sending, by the master core of each of the dies, a message to the master core of each of the other dies that specifies the determined number of enabled cores of the die; and

receiving a message, by the master core of each of the dies, from the master core of each of the other dies that specifies the determined number of enabled cores of the other die.

22. The method of claim 21, wherein said communicating with the master core of each of the other dies to determine the number of enabled cores comprises determining that one of the other master cores is not enabled if the one of the other master cores does not respond to the message from the master core within a predetermined amount of time.

23. The method of claim 13, wherein each die includes inter-core communication wires that provide the inter-core communication channels used to perform said communicating with each of the other cores of the die to determine the number of enabled cores of the die, wherein the multi-core microprocessor includes inter-die communication wires that provide the inter-die communication channels used to perform said communicating with the master core of each of the other dies to determine the number of enabled cores of the microprocessor.

24. The method of claim 13, wherein said communicating with each of the other cores of the die to determine the number of enabled cores of the die and said communicating with the master core of each of the other dies to determine the number of enabled cores of the microprocessor are performed by microcode of the master core of each die.

25. A computer program product encoded in at least one computer readable storage medium for use with a computing device configured to communicate with system memory over a system bus, the computer program product comprising:

computer readable program code embodied in said medium, for specifying a microprocessor, the computer readable program code comprising;

program code for specifying a plurality of semiconductor dies, wherein each of the dies comprises a plurality of processing cores, wherein one of the plurality of processing cores of each of the dies is designated as the master core, wherein each of the master cores is configured to;

communicate with each of the other cores of its die over inter-core communication channels to determine the number of enabled cores of the die, in response to a reset of the microprocessor; and

communicate with the master core of each of the other dies over inter-die communication channels to determine the number of enabled cores of the microprocessor, after determining the number of enabled cores of the die;

wherein the inter-core and inter-die communication channels are external to the system bus.

26. The computer program product of claim 25, wherein the at least one computer readable storage medium is selected from the set of a disk, tape, or other magnetic, optical, or electronic storage medium and a network, wire line, wireless or other communications medium.