Method and system of change evaluation of an electronic design for verification confirmation

• US 8,930,877 B1
• Filed: 06/27/2013
• Issued: 01/06/2015
• Est. Priority Date: 06/27/2013
• Status: Active Grant

• Current Assignee: Zipalog, Inc.
• Original Assignee: Zipalog, Inc.
• Inventors: Krasnicki, Michael, Deng, Yue
• Primary Examiner(s): Whitmore, Stacy
• Assistant Examiner(s): DIMYAN, MAGID Y
• Application Number:
  US13/929,007
• Publication Number:
  US 20150007124A1
• Time in Patent Office: 558 Days
• Field of Search: 716/136
• US Class Current: 716/136
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/38 Circuit design at the mixed level of analogue and digital signals
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature of the data representative of the subcomponent and determining a difference of the current signature and the banked signature.

Claims

1. A computer implemented method of change evaluation of an electronic design file for design verification confirmation prior to fabrication of an electronic circuit defined by the electronic design file, comprising the steps of:

receiving, at the processor, said electronic design file defining the electronic circuit comprised at least in part of a hierarchy of the electronic circuit having at least one subcomponent of the electronic circuit, wherein the electronic design file defines a functional level electronic design of the electronic circuit;

employing, at the processor, a banked signature of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file;

generating, at the processor, a current signature of said data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file;

determining, at the processor, a difference based at least in part upon said current signature associated with the electronic design file and said banked signature associated with the electronic design file; and

tracking, at the processor, at least one lineal subcomponent of the electronic circuit defined by the electronic design file that is hierarchically related to said at least one subcomponent of the electronic circuit defined by the electronic design file in response to said determined difference.

2. The computer implemented method of change evaluation of the functional electronic design for verification confirmation of claim 1, further comprising the step of determining a verification history of said functional electronic design.

3. The computer implemented method of change evaluation of the functional electronic design for verification confirmation of claim 1, wherein said at least one subcomponent defined by the electronic design file comprises a definition that has multiple levels of abstraction.

4. The computer implemented method of change evaluation of the functional electronic design for verification confirmation of claim 1, wherein said at least one lineal subcomponent defined by the electronic design file is for a higher level of abstraction.

5. The computer implemented method of change evaluation of the functional electronic design for verification confirmation of claim 1, wherein said at least one lineal subcomponent defined by the electronic design file is for a lower level of abstraction.

6. The computer implemented method of change evaluation of the functional electronic design for verification confirmation of claim 1, further comprising the step of receiving a verification history of said functional electronic design.

7. The computer implemented method of change evaluation of the functional electronic design for verification confirmation of claim 1, further comprising the step of receiving at least one modification of said at least one subcomponent defined by the electronic design file.

8. The computer implemented method of change evaluation of the functional electronic design for verification confirmation of claim 7, further comprising the step of evaluating an equivalence of said at least one subcomponent defined by the electronic design file and said at least one modified subcomponent defined by the electronic design file.

9. The computer implemented method of change evaluation of the functional electronic design for verification confirmation of claim 8, further comprising the step of providing a consequence log based at least in part upon said determined difference, said evaluated equivalence and said at least one lineal subcomponent defined by the electronic design file, wherein said consequence log indicates an effect upon said functional electronic design resulting from said at least one modification of said at least one subcomponent defined by the electronic design file.

10. The computer implemented method of change evaluation of the functional electronic design for verification confirmation of claim 9, further comprising the step of determining a verification delta based at least in part upon said consequence log and said verification history.

11. A computer program product embodied on a non-transitory computer usable medium, said non-transitory computer usable medium having stored thereon a sequence of instructions which, when executed by a processor causes said processor to execute a method of change evaluation of an electronic design file prior to fabrication of an electronic circuit defined by the electronic design file for design verification confirmation that has been subject to modification, said method comprising the steps of:

receiving said electronic design file defining the electronic circuit comprised at least in part of a hierarchy having at least one subcomponent of the electronic circuit, wherein the electronic design file defines a functional level electronic design of the electronic circuit;

employing a banked signature of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file;

receiving a verification history of said functional level electronic design; and

using a computer processor to receive at least one modification of said at least one subcomponent of the electronic circuit defined by the electronic design file;

generating a current signature of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file in response to said at least one modification;

determining a difference based at least in part upon said current signature associated with the electronic design file and said banked signature associated with the electronic design file;

tracking at least one lineal subcomponent of the electronic circuit defined by the electronic design file that is hierarchically related to said at least one subcomponent of the electronic circuit defined by the electronic design file in response to said determined difference and effected by said at least one modification of said at least one subcomponent of the electronic circuit defined by the electronic design file;

providing a consequence log based at least in part upon said determined difference and said at least one lineal subcomponent of the electronic circuit defined by the electronic design file, wherein said consequence log indicates an effect upon said functional level electronic design resulting from said at least one modification of said at least one subcomponent of the electronic circuit defined by the electronic design file; and

assessing a verification delta based at least in part upon said consequence log and said verification history.

12. The computer program product embodied on the non-transitory computer usable medium of claim 11, wherein said hierarchical relations comprises at least a system level, an architectural level, a dataflow level, an electrical level, a device level and a technology level.

13. A computer-based system of confirming design verification based on change evaluation of an electronic design file prior to fabrication of an electronic circuit defined by the electronic design file that has been subject to modification, comprising:

a computer processor to execute a set of program code instructions;

a memory to hold said program code instructions, in which said program code instructions comprises program code;

to receive said electronic design file defining the electronic circuit comprised at least in part of a hierarchy of the electronic circuit having at least one subcomponent of the electronic circuit, wherein the electronic design file defines a functional level electronic design of the electronic circuit;

to employ a banked signature of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file;

to use said computer processor to receive at least one modification of said at least one subcomponent of the electronic circuit defined by the electronic design file;

to generate a current signature of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file in response to said at least one modification;

to determine a difference based at least in part upon said current signature associated with the electronic design file and said banked signature associated with the electronic design file;

to evaluate an equivalence base at least in part upon said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one modified subcomponent of the electronic circuit defined by the electronic design file in response to determined difference;

to track at least one lineal subcomponent of the electronic circuit defined by the electronic design file that is hierarchically related to said at least one modified subcomponent of the electronic circuit defined by the electronic design file in response to said determined difference and said evaluated equivalence; and

to provide a consequence log based at least in part upon said determined difference, said evaluated equivalence and said at least one lineal subcomponent of the electronic circuit defined by the electronic design file, wherein said consequence log indicates an effect upon said electronic design resulting from said at least one modification of said at least one subcomponent.