Manufacturing method of semiconductor device

• US 8,932,913 B2
• Filed: 04/13/2012
• Issued: 01/13/2015
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sasagawa, Shinya, Ishizuka, Akihiro
• Primary Examiner(s): Kuo, Wensing
• Assistant Examiner(s): WHITE, SHAKA SHAKAR
• Application Number:
  US13/446,022
• Publication Number:
  US 20120270375A1
• Time in Patent Office: 1,005 Days
• Field of Search: None
• US Class Current: 438/149
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To provide a semiconductor device which prevents defects and achieves miniaturization. A projecting portion or a trench (a groove portion) is formed in an insulating layer and a channel formation region of a semiconductor layer is provided in contact with the projecting portion or the trench, so that the channel formation region is extended in a direction perpendicular to a substrate. Thus, miniaturization of the transistor can be achieved and an effective channel length can be extended. In addition, before formation of the semiconductor layer, an upper-end corner portion of the projecting portion or the trench with which the semiconductor layer is in contact is subjected to round chamfering, so that a thin semiconductor layer can be formed with good coverage.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating layer;

etching the insulating layer to form a first region with a first thickness and second regions with a second thickness smaller than the first thickness;

processing an edge portion of the first region into a curved shape with rare gas plasma treatment;

forming an oxide semiconductor layer over the insulating layer so as to be in contact with at least the first region having the curved shape;

forming a source electrode and a drain electrode electrically connected to the oxide layer;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer so that the gate electrode faces the side surfaces of the first region with the oxide semiconductor layer and the gate insulating layer interposed between the gate electrode and the side surfaces of the first region,

wherein the first region is positioned between the second regions, and

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a crystal whose c-axis changes with the curved shape of the first region so that a direction of the c-axis is a direction parallel to a normal vector of the curved shape of the first region.

3. The method for manufacturing a semiconductor device according to claim 1,

wherein the oxide semiconductor layer includes a crystal having a c-axis parallel to a normal vector of each of a side surface of the first region and top surfaces of the second regions.

13. The method for manufacturing a semiconductor device according to claim 1, wherein the curved shape has a radius of curvature of greater than or equal to 20 nm and less than or equal to 60 nm.

4. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating layer;

etching the insulating layer to form a first region with a first thickness and second regions with a second thickness smaller than the first thickness;

processing an edge portion of the first region into a curved shape with rare gas plasma treatment;

forming an oxide semiconductor layer in contact with a top surface, side surfaces, and the edge portion with the curved shape of the first region and parts of the second regions;

forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer so that the gate electrode faces the side surfaces of the first region with the oxide semiconductor layer and the gate insulating layer interposed between the gate electrode and the side surfaces of the first region,

wherein the first region is positioned between the second regions, and

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the oxide semiconductor layer includes a crystal whose c-axis changes with the curved shape of the first region so that a direction of the c-axis is a direction parallel to a normal vector of the curved shape of the first region.

6. The method for manufacturing a semiconductor device according to claim 4, wherein the oxide semiconductor layer includes a crystal having a c-axis parallel to a normal vector of each of a side surface of the first region and top surfaces of the second regions.

14. The method for manufacturing a semiconductor device according to claim 4, wherein the curved shape has a radius of curvature of greater than or equal to 20 nm and less than or equal to 60 nm.

7. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating layer;

forming a metal layer over the insulating layer;

forming a resist mask over the metal layer;

patterning the metal layer with the resist mask;

removing the resist mask after patterning the metal layer;

etching the insulating layer with the patterned metal layer used as a mask to form a first region with a first thickness and second regions with a second thickness smaller than the first thickness, the first region being below the patterned metal layer;

removing the patterned metal layer and processing an edge portion of the first region into a curved shape, by dry etching on the patterned metal layer with one or both of a gas containing fluorine and a gas containing chlorine;

forming an oxide semiconductor layer in contact with a top surface, side surfaces, and the edge portion with the curved shape of the first region and parts of the second regions;

forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer so that the gate electrode faces the side surfaces of the first region with the oxide semiconductor layer and the gate insulating layer interposed between the gate electrode and the side surfaces of the first region,

wherein the first region is positioned between the second regions, and

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the oxide semiconductor layer includes a crystal whose c-axis changes with the curved shape of the first region so that a direction of the c-axis is a direction parallel to a normal vector of the curved shape of the first region.

9. The method for manufacturing a semiconductor device according to claim 7, wherein the oxide semiconductor layer includes a crystal having a c-axis parallel to a normal vector of each of a side surface of the first region and top surfaces of the second regions.

15. The method for manufacturing a semiconductor device according to claim 7, wherein the curved shape has a radius of curvature of greater than or equal to 20 nm and less than or equal to 60 nm.

10. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating layer;

forming a resist mask over the insulating layer;

performing heat treatment on the resist mask to obtain a resist mask having a curved surface;

etching the insulating layer with the resist mask having the curved surface to form a first region with a first thickness and second regions with a second thickness smaller than the first thickness, the first region being below the resist mask having the curved surface and having an edge portion processed into a curved shape;

forming an oxide semiconductor layer in contact with a top surface, side surfaces, and the edge portion with the curved shape of the first region and parts of the second regions;

forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer so that the gate electrode faces the side surfaces of the first region with the oxide semiconductor layer and the gate insulating layer interposed between the gate electrode and the side surfaces of the first region,

wherein the first region is positioned between the second regions, and

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the oxide semiconductor layer includes a crystal whose c-axis changes with the curved shape so that a direction of the c-axis is a direction parallel to a normal vector of the curved shape.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the oxide semiconductor layer includes a crystal having a c-axis parallel to a normal vector of each of a side surface of the first region and top surfaces of the second regions.

16. The method for manufacturing a semiconductor device according to claim 10, the curved shape has a radius of curvature of greater than or equal to 20 nm and less than or equal to 60 nm.