Power semiconductor device

• US 8,932,946 B2
• Filed: 02/19/2014
• Issued: 01/13/2015
• Est. Priority Date: 09/12/2012
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Saito, Wataru
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US14/183,765
• Publication Number:
  US 20140167838A1
• Time in Patent Office: 328 Days
• Field of Search: 438294-295, 438/585, 257330-331, 257/259, 257/500, 257/502, 257/510
• US Class Current: 438/585
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference

Abstract

According to one or more embodiments of the present invention, a method for driving a power semiconductor device that has a source electrode, a drain electrode, a semiconductor layer formed between the source electrode and the drain electrode, a plurality of gate electrodes formed within the semiconductor layer, and a plurality of conductive layers that are formed between the gate electrodes and the drain electrode and in electrical communication with the gate electrodes. The method comprises providing a first electric potential to the source electrode, providing a second electric potential to the drain electrode, providing a third electric potential to the gate electrodes, providing a first electric potential to at least one of the conductive layers, and providing a third electric potential to at least another one of the conductive layers.

Claims

1. A method for driving a semiconductor device that has a source electrode, a drain electrode, a semiconductor layer between the source electrode and the drain electrode, a plurality of gate electrodes within the semiconductor layer, and a plurality of conductive layers that are between the gate electrodes and the drain electrode, the method comprising:

providing a first electric potential to the source electrode;

providing a second electric potential to the drain electrode;

providing a third electric potential to the gate electrodes;

providing the first electric potential to at least one conductive layer of the plurality of conductive layers; and

providing the third electric potential to at least another one of the plurality of conductive layers.

2. The method according to claim 1, wherein

the at least one conductive layer to which the first electric potential is provided and the conductive layers to which the third electric potential is provided are arranged alternately.

3. The method according to claim 2, wherein

the conductive layers extend in a direction that is substantially perpendicular to a plane of the drain electrode.

4. The method according to claim 1, wherein

the at least one conductive layer to which the first electric potential is provided adjoins the conductive layers to which the third electric potential is provided.

5. The method according to claim 1, wherein

the at least one conductive layer to which the first electric potential is provided is arranged between the conductive layers to which the third electric potential is provided.

6. The method according to claim 1, wherein

the conductive layers to which the third electric potential is provided adjoins and is surrounded by the at least one conductive layer to which the first electric potential is provided.

7. A method for driving a semiconductor device that has a source electrode, a drain electrode, a semiconductor layer between the source electrode and the drain electrode, a plurality of gate electrodes within the semiconductor layer, and a plurality of conductive layers that are between the gate electrodes and the drain electrode, the method comprising:

providing a first electric potential to the source electrode;

providing a second electric potential to the drain electrode;

providing a third electric potential to the gate electrodes;

providing the first electric potential to a first conductive layer of the plurality of conductive layers; and

providing the third electric potential to a second conductive layer and a third conductive layer of the plurality of conductive layers.

8. The method according to claim 7, wherein

the first conductive layer is layered alternatively with and the second and third conductive layers.

9. The method according to claim 8, wherein

the first, the second, and the third conductive layers extend in a direction that is substantially perpendicular to a plane of the drain electrode.

10. The method according to claim 7, wherein

the first conductive layer adjoins the second and third conductive layers.

11. The method according to claim 7, wherein

the first conductive layer is arranged between the second and third conductive layers.

12. The method according to claim 7, wherein

the second and third conductive layers adjoin and are positioned on opposing sides of the first conductive layer.