Dual-plane memory array
First Claim
1. A memory array comprising:
- a plurality of conductor structures, each conductor structure having a top wire segment extending in a first direction, a middle wire segment extending in a second direction at an angle from the first direction, a bottom wire segment extending in a direction opposite to the first direction, and a via connecting the top, middle, and bottom wire segments;
a plurality of memory cells in an upper plane formed at intersections of the middle wire segment of each conductor structure with the top wire segments of neighboring conductor structures; and
a plurality of memory cells in a lower plane formed at intersections of the middle wire segment of each conductor structure with the bottom wire segments of neighboring conductor structures.
2 Assignments
0 Petitions
Accused Products
Abstract
A memory array has a plurality of conductor structures. Each conductor structure has a top wire segment extending in a first direction, a middle wire segment extending in a second direction at an angle from the first direction, a bottom wire segment extending in a direction opposite to the first direction, and a via connecting the top, middle, and bottom wire segments. A plurality of memory cells in an upper plane of the memory array are formed at intersections of the middle wire segment of each conductor structure with the top wire segments of neighboring conductor structures, and a plurality of memory cells in a lower plane are formed at intersections of the middle wire segment of each conductor structure with the bottom wire segments of neighboring conductor structures.
16 Citations
15 Claims
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1. A memory array comprising:
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a plurality of conductor structures, each conductor structure having a top wire segment extending in a first direction, a middle wire segment extending in a second direction at an angle from the first direction, a bottom wire segment extending in a direction opposite to the first direction, and a via connecting the top, middle, and bottom wire segments; a plurality of memory cells in an upper plane formed at intersections of the middle wire segment of each conductor structure with the top wire segments of neighboring conductor structures; and a plurality of memory cells in a lower plane formed at intersections of the middle wire segment of each conductor structure with the bottom wire segments of neighboring conductor structures. - View Dependent Claims (2, 3, 4, 5)
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6. A memory array comprising:
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a plurality of top wire segments extending in a first direction in a top layer; a plurality of middle wire segments in a middle layer extending in a second direction at an angle to the first direction; a plurality of bottom wire segments in a bottom layer extending in a direction opposite to the first direction; a plurality of memory cells in an upper plane formed at intersections of plurality of the top wire segments with the plurality of middle wire segments; a plurality of memory cells in a lower plane formed at intersections of the plurality of middle wire segments with the plurality of bottom wire segments; and a plurality of vias, each via connecting a top wire segment, a middle wire segment, and a bottom wire segment. - View Dependent Claims (7, 8, 9, 10)
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11. A memory array comprising:
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a plurality of conductor structures, each conductor structure having a top wire segment, a middle wire segment, and bottom wire segment connected together by a via, with top and bottom wire segments extending in opposite directions and the middle wire segment extending in a direction perpendicular to the top and bottom wire segments; a plurality of memory cells disposed in an upper plane and a lower plane, each memory cell in the upper plane being formed at an intersection of a top wire segment of a conductor structure with a middle wire segment of another conductor structure, and each memory cell in the lower plane being formed at an intersection of a bottom wire segment of a conductor structure with a middle wire segment of another plurality of conductor structure; and decoders disposed in a plane under the conductor structures for decoding addresses of the vias of two conductor structures for accessing a memory cell formed at an intersection of the two conductor structures. - View Dependent Claims (12, 13, 14, 15)
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Specification