3D non-volatile memory with metal silicide interconnect

• US 8,933,502 B2
• Filed: 11/21/2011
• Issued: 01/13/2015
• Est. Priority Date: 11/21/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Higashitani, Masaaki, Rabkin, Peter
• Primary Examiner(s): SANDVIK, BENJAMIN P
• Application Number:
  US13/301,597
• Publication Number:
  US 20130126957A1
• Time in Patent Office: 1,149 Days
• Field of Search: None
• US Class Current: 257/326
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.

Claims

1. A 3D stacked non-volatile memory device, comprising:

a substrate;

a stacked non-volatile memory cell array carried by the substrate, the stacked non-volatile memory cell array comprising;

alternating stacked layers of dielectric and conductive material, the alternating stacked layers comprising a topmost layer and a bottommost layer,

first and second cell areas,

the first and second cell areas comprising rows of vertical columns, the vertical columns comprise NAND cells and extend through the alternating stacked layers of dielectric and conductive material, and

at least one interconnect area which is adjacent to and between the first and second cell areas, the at least one interconnect area comprising first and second insulation-filled slits which run a full length and height of the stacked non-volatile memory cell array and at least one metal silicide interconnect between the first and second insulation-filled slits, the at least one metal silicide interconnect extends through the alternating stacked layers of dielectric and conductive material, from the bottommost layer to the topmost layer and does not comprise vertical columns of NAND cells, the first insulation-filled slit is adjacent to the first cell area, the second insulation-filled slit is adjacent to the second cell area, and the at least one metal silicide interconnect is adjacent to at least one of the first or second insulation-filled slits;

at least one lower metal layer carried by the substrate, below the stacked non-volatile memory cell array; and

at least one upper metal layer, above the stacked non-volatile memory cell array, the at least one metal silicide interconnect is electrically connected to at least one contact structure of the at least one lower metal layer, and to at least one contact structure of the at least one upper metal layer, and the at least one contact structure of the at least one lower metal layer is directly below the stacked non-volatile memory cell array.

2. The 3D stacked non-volatile memory device of claim 1, wherein:

the at least one metal silicide interconnect is adjacent to both of the first and second insulation-filled slits.

3. The 3D stacked non-volatile memory device of claim 1, wherein:

each vertical column is in a straight NAND string; and

the first and second cell areas comprise insulation-filled slits which extend between each row of vertical columns.

4. The 3D stacked non-volatile memory device of claim 1, wherein:

pairs of the vertical columns are in U-shaped NAND strings; and

the first and second cell areas comprise insulation-filled slits which extend between rows of vertical columns of straight NAND strings which are in a common U-shaped NAND string.

5. The 3D stacked non-volatile memory device of claim 1, further comprising:

circuitry carried by the substrate, directly below the stacked non-volatile memory cell array, the at least one metal silicide interconnect electrically connects the circuitry to the at least one upper metal layer.

6. The 3D stacked non-volatile memory device of claim 1, wherein:

the first and second insulation-filled slits of the at least one interconnect area are parallel to one another.

7. The 3D stacked non-volatile memory device of claim 1, wherein:

the first and second areas are on opposing sides of the at least one interconnect area.

8. The 3D stacked non-volatile memory device of claim 1, wherein:

the stacked non-volatile memory cell array is arranged in a plurality of subarrays in a plane without word line hook-up and transfer areas between the subarrays.

9. The 3D stacked non-volatile memory device of claim 1, further comprising:

circuitry comprising a high-voltage transistor for a charge pump, cell source discharge or other power circuitry, the circuitry is carried by the substrate directly below the stacked non-volatile memory cell array, and is electrically connected to the at least one upper metal layer by the at least one metal silicide interconnect.

10. The 3D stacked non-volatile memory device of claim 1, wherein:

the at least one metal silicide interconnect comprises a terraced portion by which the at least one metal silicide interconnect is electrically connected to the at least one contact structure of the at least one upper metal layer.

11. The 3D stacked non-volatile memory device of claim 6, wherein:

the at least one interconnect area comprises a third insulation-filled slit which runs a full length and height of the stacked non-volatile memory cell array, the third insulation-filled slit is between and parallel with the first and second insulation-filled slits;

the at least one metal silicide interconnect comprises first and second regions of metal silicide;

the first region of metal silicide extends between the first and second insulation-filled slits and is adjacent to the first insulation-filled slit;

the second region of metal silicide extends between the second and third insulation-filled slits and is adjacent to the second insulation-filled slit;

the first and second regions of metal silicide are insulated from one another by the third insulation-filled slit; and

each of the first and second regions of metal silicide is electrically connected to a respective contact structure of the at least one lower metal layer, and to a respective contact structure of the at least one upper metal layer.

12. The 3D stacked non-volatile memory device of claim 6, wherein:

the at least one interconnect area comprises a transverse insulation-filled slit which runs a full height of the stacked non-volatile memory cell array, the transverse insulation-filled slit extends transversely to the first and second insulation-filled slits; and

the at least one metal silicide interconnect comprises a first region of metal silicide on one side of the transverse insulation-filled slit, and a second region of metal silicide on another side of the transverse insulation-filled slit, the first and second regions of metal silicide connect respective contact structures of the at least one lower metal layer to respective contact structures of the at least one upper metal layer.

13. The 3D stacked non-volatile memory device of claim 1, wherein:

the stacked non-volatile memory cell array comprises an etch stop layer below the alternating stacked layers of dielectric and conductive material; and

the at least one contact structure of the at least one lower metal layer extends upward through the etch stop layer to the at least one metal silicide interconnect.

14. The 3D stacked non-volatile memory device of claim 13, wherein:

the first and second insulation-filled slits, extend down to the etch stop layer; and

the at least one metal silicide interconnect extends from the etch stop layer to the topmost layer of the alternating stacked layers.

15. The 3D stacked non-volatile memory device of claim 1, wherein:

the stacked non-volatile memory cell array is arranged in a plurality of subarrays in a plane; and

the at least one interconnect area comprises at least one metal silicide interconnect extending between insulation-filled slits of the at least one interconnect area, in each of the subarrays.

16. The 3D stacked non-volatile memory device of claim 15, further comprising:

circuitry for each subarray, the circuitry for each subarray is carried by the substrate directly below each subarray, the at least one metal silicide interconnect in each of the subarrays electrically connects the circuitry for the subarray to the at least one upper metal layer.

17. The 3D stacked non-volatile memory device of claim 16, wherein:

the circuitry comprises sense amplifier circuitry for each subarray.

18. The 3D stacked non-volatile memory device of claim 1, wherein:

each vertical column comprise a select gate above the NAND cells of the vertical column.

19. The 3D stacked non-volatile memory device of claim 1, wherein:

the at least one metal silicide interconnect is located partway across the stacked non-volatile memory cell array, intermediate to edges of the stacked non-volatile memory cell array.

20. A 3D stacked non-volatile memory device, comprising:

a substrate;

a stacked non-volatile memory cell array carried by the substrate, the stacked non-volatile memory cell array comprising alternating stacked layers of dielectric and conductive material, and a cell area comprising rows of vertical columns, the vertical columns comprise NAND cells and extend through the alternating stacked layers of dielectric and conductive material between insulation-filled slits of the cell area;

a peripheral area of the substrate, lateral of the stacked non-volatile memory cell array, the peripheral area comprising alternating stacked layers of dielectric and conductive material and at least one metal silicide interconnect, the at least one metal silicide interconnect extending between insulation-filled slits of the peripheral area and through the alternating stacked layers of dielectric and conductive material of the peripheral area, from a bottommost layer of the alternating stacked layers of the peripheral area to a topmost layer of the alternating stacked layers of the peripheral area, the peripheral area does not comprise vertical columns of NAND cells;

at least one lower metal layer carried by the substrate, below the peripheral area; and

at least one upper metal layer, above the peripheral area, the at least one metal silicide interconnect is electrically connected to at least one contact structure of the at least one lower metal layer, and to at least one contact structure of the at least one upper metal layer, and the at least one contact structure of the at least one lower metal layer is directly below the peripheral area, wherein;

the insulation-filled slits of the peripheral area include a pair of parallel insulation-filled slits and at least one transverse insulation-filled slit which extends transversely to the pair of parallel insulation-filled slits; and

the at least one metal silicide interconnect comprises one region of metal silicide on one side of the at least one transverse insulation-filled slit, and another region of metal silicide on another side of the at least one transverse insulation-filled slit, the one region of metal silicide on the one side of the at least one transverse insulation-filled slit and the another region of metal silicide on the another side of the at least one transverse insulation-filled slit connect respective contact structures of the at least one lower metal layer to respective contact structures of the at least one upper metal layer.

21. The 3D stacked non-volatile memory device of claim 20, further comprising:

circuitry carried by the substrate, directly below the peripheral area, the at least one metal silicide interconnect electrically connects the circuitry to the at least one upper metal layer.

22. The 3D stacked non-volatile memory device of claim 20, wherein:

the peripheral area comprises an etch stop layer;

the at least one metal silicide interconnect extends from the etch stop layer to the topmost layer of the alternating stacked layers of the peripheral area; and

the at least one contact structure of the at least one lower metal layer extends upward through the etch stop layer to the at least one metal silicide interconnect.

23. The 3D stacked non-volatile memory device of claim 22, wherein:

the insulation-filled slits of the peripheral area extend down to the etch stop layer; and

the at least one metal silicide interconnect extends from the etch stop layer to the topmost layer of the alternating stacked layers of the peripheral area.

24. The 3D stacked non-volatile memory device of claim 20, wherein:

each vertical column comprise a select gate above the NAND cells of the vertical column.

25. The 3D stacked non-volatile memory device of claim 20, wherein:

the at least one metal silicide interconnect is located partway across the stacked non-volatile memory cell array, intermediate to edges of the stacked non-volatile memory cell array.

26. A 3D stacked non-volatile memory device, comprising:

a substrate;

a stacked non-volatile memory cell array carried by the substrate, the stacked non-volatile memory cell array comprising alternating stacked layers of dielectric and conductive material, and a cell area comprising rows of vertical columns, the vertical columns comprise NAND cells and extend through the alternating stacked layers of dielectric and conductive material between insulation-filled slits of the cell area;

a peripheral area of the substrate, lateral of the stacked non-volatile memory cell array, the peripheral area comprising alternating stacked layers of dielectric and conductive material and at least one metal silicide interconnect, the at least one metal silicide interconnect extending between insulation-filled slits of the peripheral area and through the alternating stacked layers of dielectric and conductive material of the peripheral area, from a bottommost layer of the alternating stacked layers of the peripheral area to a topmost layer of the alternating stacked layers of the peripheral area, the peripheral area does not comprise vertical columns of NAND cells;

at least one lower metal layer carried by the substrate, below the peripheral area; and

at least one upper metal layer, above the peripheral area, the at least one metal silicide interconnect is electrically connected to at least one contact structure of the at least one lower metal layer, and to at least one contact structure of the at least one upper metal layer, and the at least one contact structure of the at least one lower metal layer is directly below the peripheral area;

wherein the at least one metal silicide interconnect comprises a terraced portion by which the at least one metal silicide interconnect is electrically connected to the at least one contact structure of the at least one upper metal layer.

27. A 3D stacked non-volatile memory device, comprising:

a substrate;

a stacked non-volatile memory cell array carried by the substrate, the stacked non-volatile memory cell array comprising alternating stacked layers of dielectric and conductive material, and a cell area comprising rows of vertical columns, the vertical columns comprise NAND cells and extend through the alternating stacked layers of dielectric and conductive material between insulation-filled slits of the cell area;

a peripheral area of the substrate, lateral of the stacked non-volatile memory cell array, the peripheral area comprising alternating stacked layers of dielectric and conductive material and at least one metal silicide interconnect, the at least one metal silicide interconnect extending between insulation-filled slits of the peripheral area and through the alternating stacked layers of dielectric and conductive material of the peripheral area, from a bottommost layer of the alternating stacked layers of the peripheral area to a topmost layer of the alternating stacked layers of the peripheral area, the peripheral area does not comprise vertical columns of NAND cells;

at least one lower metal layer carried by the substrate, below the peripheral area; and

at least one upper metal layer, above the peripheral area, the at least one metal silicide interconnect is electrically connected to at least one contact structure of the at least one lower metal layer, and to at least one contact structure of the at least one upper metal layer, and the at least one contact structure of the at least one lower metal layer is directly below the peripheral area;

wherein;

the at least one metal silicide interconnect comprises respective regions of metal silicide;

each respective region of metal silicide extends between a different pair of the insulation-filled slits of the peripheral area;

the respective regions of metal silicide are insulated from one another by the insulation-filled slits of the peripheral area; and

each respective region of metal silicide is electrically connected to a respective contact structure of the at least one lower metal layer, and to a respective contact structure of the at least one upper metal layer.