Memory with isolation structure

• US 8,933,508 B2
• Filed: 03/13/2013
• Issued: 01/13/2015
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US13/799,084
• Publication Number:
  US 20130248958A1
• Time in Patent Office: 671 Days
• Field of Search: 257/301, 257329-333, 257/520, 257/E29.257, 257/E29.26
• US Class Current: 257/330
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A recessed transistor construction is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In some embodiments, a gate of the recessed transistor construction is grounded. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell.

Claims

1. An apparatus comprising:

a substrate having a doping concentration;

a memory cell comprising a charge storage device and a recessed access device, wherein the recessed access device extends into the substrate and is configured to induce a first depletion region in the substrate; and

an isolation structure configured to isolate the memory cell from an adjacent memory cell, wherein the apparatus is configured such that during operation the isolation structure receives a bias voltage that together with the doping concentration of the substrate induces a second depletion region in the substrate that merges with the first depletion region.

2. The apparatus of claim 1, wherein the memory cell comprises a 4.5F2 dynamic random access memory (DRAM) cell.

3. The apparatus of claim 1, wherein the isolation structure comprises a transistor having a gate electrically connected to ground.

4. The apparatus of claim 1, wherein the recessed access device comprises a two-sided access transistor.

5. The apparatus of claim 1, wherein the substrate comprises a p-doped substrate.

6. The apparatus of claim 1, wherein the recessed access device comprises a source/drain region shared with another recessed access device, and wherein the source/drain region is electrically connected to a digit line.

7. The apparatus of claim 6, wherein the adjacent memory cell comprises a recessed access device having a source/drain region that is electrically connected to a different digit line.

8. The apparatus of claim 1, wherein the charge storage device comprises a capacitor.

9. The apparatus of claim 1, wherein the second depletion region in the substrate that merges with the first depletion region substantially reduces leakage current between the memory cell and the adjacent memory cell.

10. An apparatus comprising:

a substrate having a doping concentration;

a first memory cell comprising a first access transistor, wherein first the access transistor is configured to induce a first depletion region in the substrate;

an isolation structure configured to receive a bias voltage that together with the doping concentration of the substrate induces a second depletion region in the substrate that merges with the first depletion region; and

a second memory cell comprising a second access transistor, wherein the second access transistor is configured to induce a third depletion region in the substrate that merges with the second depletion region.

11. The apparatus of claim 10, wherein first access transistor comprises a two-sided surround access transistor.

12. The apparatus of claim 10, wherein first access transistor and the second access transistor are electrically connected to different digit lines.

13. The apparatus of claim 10, wherein first access transistor has a gate defining an active area of the first memory cell, and wherein the active area is oriented at an angle of about 45 degrees with respect to a digit line that is electrically connected to the first access transistor.

14. The apparatus of claim 10, wherein the apparatus comprises a dynamic random access memory (DRAM) memory device, and wherein the DRAM device comprises the first memory cell, the isolation structure, and the second memory cell.

15. The apparatus of claim 10, wherein isolation structure comprises a transistor having a gate formed within the substrate.

16. The apparatus of claim 10, wherein the first memory cell comprises a first charge storage device.

17. An apparatus comprising:

a semiconductor substrate;

a first memory cell comprising a first charge storage device and a first access device recessed in the semiconductor substrate, the first access device having a first gate;

a second memory cell comprising a second charge storage device and a second access device recessed in the semiconductor substrate;

an isolation structure between the first access device and the second access device, the isolation structure being recessed in the semiconductor substrate, the isolation structure being biased to inhibit leakage between the first memory cell and the second memory cell; and

a digit line electrically connected to the first access device of the first memory cell, wherein the first gate of the first access device defines an active area that is oriented at an angle of about 45 degrees with respect to the digit line.

18. The apparatus of claim 17, further comprising a word line configured to activate the first access device of the first memory cell, wherein the active area is oriented at an angle of about 45 degrees with respect to the word line.

19. The apparatus of claim 17, wherein the first memory cell comprises a dynamic random access memory (DRAM) cell.

20. The apparatus of claim 17, wherein the isolation structure comprises a transistor having a gate electrically connected to ground.

21. The apparatus of claim 17, wherein the isolation structure is biased to operate in a depletion mode.