Semiconductor device and method for fabricating the same
First Claim
Patent Images
1. A semiconductor device comprising:
- a device isolation structure formed in a semiconductor substrate, the device isolation structure defining an active region;
a recess channel structure disposed in the semiconductor substrate under the active region;
a first lower gate conductive layer on the surface of the recess channel structure and defining a recess;
a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, the holding layer configured to hold a shift of a seam occurring in the recess channel structure;
a second lower gate conductive layer over and directly contacting the first lower gate conductive layer and the holding layer wherein the holding layer is surrounded by the first and the second lower gate conductive layers; and
an upper gate conductive layer over the second lower gate conductive layer.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor device includes a device isolation structure, a recess channel structure, a first lower gate conductive layer conformal to the recess channel structure and defining a recess, a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, and a second lower gate conductive layer over the first lower gate conductive layer and the holding layer. The holding layer is configured to hold a shift of the seam occurring in the recess channel structure.
-
Citations
17 Claims
-
1. A semiconductor device comprising:
-
a device isolation structure formed in a semiconductor substrate, the device isolation structure defining an active region; a recess channel structure disposed in the semiconductor substrate under the active region; a first lower gate conductive layer on the surface of the recess channel structure and defining a recess; a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, the holding layer configured to hold a shift of a seam occurring in the recess channel structure; a second lower gate conductive layer over and directly contacting the first lower gate conductive layer and the holding layer wherein the holding layer is surrounded by the first and the second lower gate conductive layers; and an upper gate conductive layer over the second lower gate conductive layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A semiconductor device comprising:
-
a device isolation structure formed in a semiconductor substrate having a PMOS region and a NMOS region, the device isolation structure defining an active region; a bulb-type recess channel structure disposed in the semiconductor substrate under the active region; a lower gate electrode disposed over the active region, the lower gate electrode including a stacked structure having a first lower gate conductive layer, a holding layer, and a second lower gate conductive layer to fill the bulb-type recess channel structure, wherein the first lower gate conductive layer is formed of a polysilicon layer doped with impurity ions, the holding layer is configured to hold a shift of a seam occurring in the recess channel structure, and the second lower gate conductive layer is formed of a polysilicon layer doped with impurity ions wherein the impurity ions in the PMOS region and the NMOS region are different, wherein the second lower gate conductive layer being disposed over and directly contacting the first lower gate conductive layer and the holding layer; and an upper gate conductive layer over the second lower gate conductive layer. - View Dependent Claims (17)
-
Specification