Conductive routings in integrated circuits using under bump metallization

• US 8,933,520 B1
• Filed: 02/28/2014
• Issued: 01/13/2015
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor LLC (Analog Devices, Inc.)
• Inventors: Jergovic, Ilija, Lacap, Efren M.
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US14/194,414
• Time in Patent Office: 319 Days
• Field of Search: 257/401, 257/369, 257/758, 257/E23.01, 257/E23.011, 257/E23.021, 438/627, 438/629
• US Class Current: 257/401
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first conductive region. The under bump metallization layer has a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region. At least one of the first conductive area or the first conductive region includes a first protrusion extending toward the second conductive area or second conductive region, respectively. Conductive vias connect the first conductive region to the second conductive area and connect the second conductive region to the first conductive area, and the vias include at least one via connected to the first protrusion.

Claims

1. An integrated circuit structure comprising:

a first conductive layer disposed on a substrate and providing first electrodes and second electrodes for a distributed transistor in the substrate, wherein the first electrodes and the second electrodes are disposed on the substrate in a pattern of alternating rows;

a second conductive layer over the first conductive layer, the second conductive layer having a first conductive portion and a second conductive portion electrically isolated from the first conductive portion, wherein the first conductive portion overlies a first plurality of the first electrodes and a first plurality of the second electrodes and the second conductive portion overlies a second plurality of the first electrodes and a second plurality of the second electrodes;

a third conductive layer over the second conductive layer, the third conductive layer having a first conductive region and a second conductive region electrically isolated from the first conductive region, the first conductive region substantially located over the first conductive portion and the second conductive region substantially located over the second conductive portion;

first conductive vias connecting the first conductive region to the first plurality of the first electrodes through apertures in the first conductive portion and connecting the second conductive region to the second plurality of the second electrodes through apertures in the second conductive portion, the first conductive vias disposed with a first density per unit length along the rows;

second conductive vias connecting the first conductive portion to the second plurality of the first electrodes and connecting the second conductive portion to the first plurality of second electrodes, the second conductive vias disposed with a second density per unit length along the rows that is greater than the first density; and

a fourth conductive layer over the third conductive layer, the fourth conductive layer having a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region.

2. The integrated circuit structure of claim 1, wherein the first conductive region includes a first protrusion extending toward the second conductive region and over the second conductive portion, and the second conductive region includes a second protrusion extending toward the first conductive region and over the first conductive portion.

3. The integrated circuit structure of claim 2, wherein the first conductive region and the second conductive region comprise interdigited protrusions, the interdigited protrusions including the first protrusion and the second protrusion.

4. The integrated circuit structure of claim 2, wherein the first conductive portion and the second conductive portion lack interdigited protrusions.

5. The integrated circuit structure of claim 1, wherein the fourth conductive layer comprises an under-bump metallization layer.

6. The integrated circuit structure of claim 1, comprising third conductive vias connecting the first conductive area to the first conductive portion through apertures in the first conductive region and connecting the second conductive area to the second conductive portion through apertures in the second conductive region.

7. The integrated circuit structure of claim 6, comprising fourth conductive vias connecting the first conductive area to the second conductive region and connecting the second conductive area to the first conductive region.

8. The integrated circuit structure of claim 7, wherein the first conductive area or the first conductive region includes a protrusion extending toward the second conductive area or second conductive region, respectively, and the fourth conductive vias are in the protrusion.

9. The integrated circuit structure of claim 7, comprising an outermost passivation layer, and wherein the first conductive vias and the second conductive vias extend through the outermost passivation layer.

10. An integrated circuit structure comprising:

a first conductive layer disposed on a substrate and providing first electrodes and second electrodes for a distributed transistor in the substrate;

a second conductive layer over the first conductive layer, the second conductive layer having first conductive portions and second conductive portions electrically isolated from the first conductive portions, the first conductive portions and the second conductive portions arranged in an alternating pattern;

a third conductive layer over the second conductive layer, the third conductive layer having a first conductive region and a second conductive region electrically isolated from the first conductive region, the first conductive region located over a first plurality of the first conductive portions and a first plurality of the second conductive portions, and the second conductive region located over a second plurality of the first conductive portions and a second plurality of the second conductive portions;

first conductive vias connecting the first conductive region to the first electrodes through apertures in the first plurality of first conductive portions and connecting the second conductive region to the second electrodes through apertures in the second plurality of second conductive portions;

second conductive vias connecting the second plurality of first conductive portions to the first electrodes and connecting the first plurality of second conductive portions to the second electrodes; and

a fourth conductive layer over the third conductive layer, the fourth conductive layer having a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region.

11. The integrated circuit structure of claim 10, wherein the first conductive region includes a first protrusion extending toward the second conductive region and over the second conductive portion, and the second conductive region includes a second protrusion extending toward the first conductive region and over the first conductive portion.

12. The integrated circuit structure of claim 11, wherein the first conductive region and the second conductive region comprise interdigited protrusions, the interdigited protrusions including the first protrusion and the second protrusion.

13. The integrated circuit structure of claim 11, wherein the first conductive portion and the second conductive portion lack interdigited protrusions.

14. The integrated circuit structure of claim 10, wherein each first conductive portion overlies a plurality of the second electrodes, and each second conductive portion overlies a plurality of the first electrodes.

15. The integrated circuit structure of claim 14, wherein each first conductive portion overlies exactly one of the first electrodes and each second conductive portion overlies exactly one of the second electrodes.

16. The integrated circuit structure of claim 10, wherein the first conductive portions and the second conductive portions are arranged in a checkerboard pattern.