Register allocation for graphics processing

• US 8,933,954 B2
• Filed: 03/23/2011
• Issued: 01/13/2015
• Est. Priority Date: 03/23/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Udayakumaran, Sumesh
• Primary Examiner(s): Richer, Joni
• Application Number:
  US13/069,702
• Publication Number:
  US 20120242673A1
• Time in Patent Office: 1,392 Days
• Field of Search: 345/530, 345/536, 345/559
• US Class Current: 345/559
• CPC Class Codes: G06F 8/44 Encoding
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G09G 2360/08 Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

In general, aspects of this disclosure describe a compiler for allocation of physical registers for storing constituent scalar values of a non-scalar value. In some example, the compiler, executing on a processor, may receive an instruction for operation on a non-scalar value. The compiler may divide the instruction into a plurality of instructions for operation on constituent scalar values of the non-scalar value. The compiler may allocate a plurality of physical registers to store the constituent scalar values.

Claims

1. A method comprising:

receiving, with a processor executing a compiler, a program with at least one instruction for graphics processing for operation on at least one non-scalar value, wherein the at least one non-scalar value comprises a value that cannot be stored in a single physical register of a specified size;

dividing, with the processor executing the compiler, the at least one instruction for operation on the at least one non-scalar value into a plurality of instructions for operation on constituent scalar values of the at least one non-scalar value, wherein each one of the constituent scalar values can be stored in the single physical register of the specified size;

allocating, with the processor executing the compiler, a plurality of physical registers to store the constituent scalar values; and

recomposing, with the processor executing the compiler, the plurality of instructions for operation on the constituent scalar values into a recomposed instruction for operation on the non-scalar value, wherein the recomposed instruction includes indices to the allocated physical registers.

2. The method of claim 1, further comprising:

assigning, with the processor executing the compiler, a plurality of virtual registers to each one of the constituent scalar values,

wherein allocating the plurality of physical registers comprises allocating the plurality of physical registers based on the assigned virtual registers.

3. The method of claim 1, further comprising:

associating, with the processor executing the compiler, the allocated physical registers with one another to indicate that the constituent scalar values are constituent scalar values of the non-scalar value.

4. The method of claim 3, wherein associating the allocated physical registers with one another comprises generating an instruction that associates the allocated physical registers with one another.

5. The method of claim 4, wherein the instruction that associates the allocated physical registers with one another comprises a combine instruction.

6. The method of claim 1, wherein allocating the plurality of physical registers comprises allocating a plurality of contiguous physical registers.

7. The method of claim 1, wherein allocating the plurality of physical registers comprises allocating the plurality of physical registers based on a live range of each one of the constituent scalar values.

8. The method of claim 1, further comprising:

generating, with the processor executing the compiler, machine code for the recomposed instruction for causing a graphics processing unit (GPU) to perform functions in accordance with the instruction for operation on the non-scalar value.

9. The method of claim 1, wherein the program with the at least one instruction for graphics processing causes a graphics processing unit (GPU) to perform functions in accordance with the program.

10. A device comprising:

a plurality of physical registers that are each of a specified size; and

a processor executing a compiler that is configured to;

receive a program with at least one instruction for graphics processing for operation on at least one non-scalar value, wherein the at least one non-scalar value comprises a value that cannot be stored in the specified size of a single physical register of the plurality of physical registers;

divide the at least one instruction for operation on the at least one non-scalar value into a plurality of instructions for operation on constituent scalar values of the at least one non-scalar value, wherein each one of the constituent scalar values can be stored in the specified size of the single physical register;

allocate two or more physical registers of the plurality of physical registers to store the constituent scalar values; and

recompose the plurality of instructions for operation on the constituent scalar values into a recomposed instruction for operation on the non-scalar value, wherein the recomposed instruction includes indices to the allocated physical registers.

11. The device of claim 10, further comprising a graphics processing unit (GPU) that comprises the plurality of physical registers.

12. The device of claim 10, wherein the processor is configured to assign a plurality of virtual registers to each one of the constituent scalar values and allocate the two or more physical registers based on the assigned virtual registers.

13. The device of claim 10, wherein the processor is configured to associate the allocated two or more physical registers with one another to indicate the constituent scalar values are constituent scalar values of the non-scalar value.

14. The device of claim 13, wherein the processor is configured to generate an instruction that associates the allocated two or more physical registers with one another to associate the allocated two or more physical registers with one another.

15. The device of claim 14, wherein the instruction that associates the allocated two or more physical registers with one another comprises a combine instruction.

16. The device of claim 10, wherein the allocated two or more physical registers comprise contiguous physical registers.

17. The device of claim 10, wherein the processor is configured to allocate the two or more physical registers based on a live range of each one of the constituent scalar values.

18. The device of claim 10, further comprising a graphics processing unit (GPU), wherein the program with the at least one instruction for graphics processing causes the GPU to perform functions in accordance with the program.

19. A non-transitory computer-readable storage medium comprising instructions for a compiler that cause one or more processors to:

receive, with the compiler, a program with at least one instruction for graphics processing for operation on at least one non-scalar value, wherein the at least one non-scalar value comprises a value that cannot be stored in a single physical register of a specified size;

divide, with the compiler, the at least one instruction for operation on the at least one non-scalar value into a plurality of instructions for operation on constituent scalar values of the at least one non-scalar value, wherein each one of the constituent scalar values can be stored in the single physical register of the specified size;

allocate, with the compiler, a plurality of physical registers to store the constituent scalar values; and

recompose, with the compiler, the plurality of instructions for operation on the constituent scalar values into a recomposed instruction for operation on the non-scalar value, wherein the recomposed instruction includes indices to the allocated physical registers.

20. The non-transitory computer-readable storage medium of claim 19, further comprising instructions that cause the one or more processors to:

assign a plurality of virtual registers to each one of the constituent scalar values,

wherein the instructions that cause the one or more processors to allocate the plurality of physical registers comprise instructions that cause the one or more processors to allocate the plurality of physical registers based on the assigned virtual registers.

21. The non-transitory computer-readable storage medium of claim 19, further comprising instructions that cause the one or more processors to:

associate the allocated physical registers with one another to indicate that the constituent scalar values are constituent scalar values of the non-scalar value.

22. The non-transitory computer-readable storage medium of claim 21, wherein the instructions that cause the one or more processors to associate the allocated physical registers with one another comprise instructions that cause the one or more processors to generate an instruction that associates the allocated physical registers with one another.

23. The non-transitory computer-readable storage medium of claim 22, wherein the instruction that associates the allocated physical registers comprises a combine instruction.

24. The non-transitory computer-readable storage medium of claim 19, wherein the instructions that cause the one or more processors to allocate the plurality of physical registers comprise instructions that cause the one or more processors to allocate a plurality of contiguous physical registers.

25. The non-transitory computer-readable storage medium of claim 19, wherein the instructions that cause the one or more processors to allocate the plurality of physical registers comprise instructions that cause the one or more processors to allocate the plurality of physical registers based on a live range of each one of the constituent scalar values.

26. The non-transitory computer-readable storage medium of claim 19, wherein the program with the at least one instruction for graphics processing causes a graphics processing unit (GPU) to perform functions in accordance with the program.

27. A device comprising:

means for receiving, with a processor executing a compiler, a program with at least one instruction for graphics processing for operation on at least one non-scalar value, wherein the at least one non-scalar value comprises a value that cannot be stored in a single physical register of a specified size;

means for dividing, with the processor executing the compiler, the at least one instruction for operation on the at least one non-scalar value into a plurality of instructions for operation on constituent scalar values of the at least one non-scalar value, wherein each one of the constituent scalar values can be stored in the single physical register of the specified size;

means for allocating, with the processor executing the compiler, a plurality of physical registers to store the constituent scalar values; and

means for recomposing, with the processor executing the compiler, the plurality of instructions for operation on the constituent scalar values into a recomposed instruction for operation on the non-scalar value, wherein the recomposed instruction includes indices to the allocated physical registers.

28. The device of claim 27, further comprising:

means for assigning a plurality of virtual registers to each one of the constituent scalar values,

wherein the means for allocating the plurality of physical registers comprises means for allocating the plurality of physical registers based on the assigned virtual registers.

29. The device of claim 27, further comprising:

means for associating the allocated physical registers with one another to indicate that the constituent scalar values are constituent scalar values of the non-scalar value.

30. The device of claim 29, wherein the means for associating the allocated physical registers with one another comprises means for generating an instruction that associates the allocated physical registers with one another.

31. The device of claim 30, wherein the instruction that associates the allocated physical registers with one another comprises a combine instruction.

32. The device of claim 27, wherein the means for allocating the plurality of physical registers comprises means for allocating a plurality of contiguous physical registers.

33. The device of claim 27, wherein the means for allocating the plurality of physical registers comprises means for allocating the plurality of physical registers based on a live range of each one of the constituent scalar values.

34. The device of claim 27, further comprising a graphics processing unit (GPU), wherein the program with the at least one instruction for graphics processing causes the GPU to perform functions in accordance with the program.