Balanced method for programming multi-layer cell memories

• US 8,934,292 B2
• Filed: 03/18/2011
• Issued: 01/13/2015
• Est. Priority Date: 03/18/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Costa, Xiying, Nian, Yibo, Scheuerlein, Roy, Liu, Tz-Yi, Gorla, Chandrasekhar Reddy
• Primary Examiner(s): Nguyen, Vanthu
• Assistant Examiner(s): ALROBAIE, KHAMDAN N
• Application Number:
  US13/051,885
• Publication Number:
  US 20120236624A1
• Time in Patent Office: 1,397 Days
• Field of Search: 365/46, 365/100, 365/148, 365/158, 365/163
• US Class Current: 365/163
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5664 using organic memory material storage elements
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0071 Write using write potential applied to access device gate
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure

Abstract

Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in the programming and then applying a pulse having the determined set electrical characteristics. Reset programming, which transitions the memory cell to a higher resistance state, is accomplished by determining an appropriate programming voltage and optionally current limit for the state to be achieved in the programming and then applying a pulse having the determined electrical characteristics. The algorithm used to determine the appropriate set or reset programming voltage and current values provides for effective programming without stressing the memory element. The electrical characteristics for programming pulses may be stored in a data table used in a table look up algorithm.

Claims

1. A method of writing data to a multilevel cell resistance memory device, comprising:

receiving data to be written to the memory device;

selecting a memory cell to which at least a portion of the received data is to be written;

determining a current resistance state of the selected memory cell;

determining an objective resistance state for representing data to be written to the selected memory cell;

determining whether the writing of data to the selected memory cell will involve increasing or decreasing resistance of the selected memory cell based on the current resistance state and the objective resistance state;

determining electrical characteristics for a programming pulse that will transform the resistance state of the selected memory cell to the objective resistance state based on the objective resistance state and whether the writing of data to the selected memory cell will involve increasing or decreasing resistance of the selected memory cell; and

applying to the selected memory cell a programming pulse having the determined electrical characteristics;

wherein the electrical characteristics of the programming pulse are configured to control both a current and a voltage of the memory cell to maintain substantially constant power dissipation in the selected memory cell while applying the programming pulse to the selected memory cell.

2. The method of claim 1, wherein determining electrical characteristics for a programming pulse comprises determining a voltage and a current limit for the programming pulse.

3. The method of claim 1, wherein determining electrical characteristics for a programming pulse comprises determining a voltage and a current limit for the programming pulse when it is determined that the writing of data to the selected memory cell will involve decreasing resistance of the selected memory cell, and determining a voltage for the programming pulse when it is determined that the writing of data to the selected memory cell will involve increasing resistance of the selected memory cell.

4. The method of claim 1, further comprising:

determining a duration for a programming pulse based on the objective resistance state and whether the writing of data to the selected memory cell will involve increasing or decreasing resistance of the selected memory cell,

wherein applying to the selected memory cell a programming pulse having the determined electrical characteristics comprises applying such a programming pulse for the determined duration.

5. The method of claim 1, wherein determining electrical characteristics for a programming pulse comprises performing a table look up operation using as inputs the objective resistance state and whether the writing of data to the selected memory cell will involve increasing or decreasing resistance of the selected memory cell and obtaining as an output the electrical characteristics.

6. The method of claim 1, further comprising determining whether the current resistance state is within threshold limits of the objective resistance state, wherein applying to the selected memory cell a programming pulse having the determined electrical characteristics comprises applying such a programming pulse to the selected memory cell when the current resistance state is not within the threshold limits of the objective resistance state and not applying a programming pulse to the selected memory cell when the current resistance state is within the threshold limits of the objective resistance state.

7. The method of claim 1, further comprising:

determining a resulting resistance state of the selected memory cell after application of the programming pulse;

determining whether the resulting resistance state is within threshold limits of the objective state; and

reapplying to the selected memory cell a programming pulse having the determined electrical characteristics when the resulting resistance state is not within the threshold limits of the objective state.

8. The method of claim 1, further comprising:

determining a resulting resistance state of the selected memory cell after application of the programming pulse;

determining whether the resulting resistance state is within threshold limits of the objective state; and

determining electrical characteristics for a second programming pulse that will transform the resistance state of the selected memory cell to the objective resistance state based on the determined resulting resistance state and the objective resistance state; and

applying to the selected memory cell a second programming pulse having the determined electrical characteristics for a second programming pulse.

9. The method of claim 1,

wherein determining electrical characteristics for a programming pulse that will transform the resistance state of the selected memory cell to the objective resistance state comprises determining a number of programming pulses and corresponding electrical characteristics for each of the number of programming pulse which when applied in series will transform the resistance state of the selected memory cell to the objective resistance state, and

wherein applying to the selected memory cell a programming pulse having the determined electrical characteristics comprises applying to the selected memory cell the number of programming pulses each having the corresponding electrical characteristics.

10. The method of claim 1, wherein the selected memory cell comprises a variable resistance material selected from the group consisting of an antifuse dielectric, fuse, diode and antifuse dielectric arranged in a series, a polysilicon memory effect material, a metal oxide or switchable complex metal oxide material, a carbon nanotube material, a graphene switchable resistivity material, a phase change material, a conductive bridge element, an electrolyte switching material, a switchable polymer material, or carbon resistivity switching material, such as amorphous, polycrystalline or microcrystalline carbon or graphite material.

11. The method of claim 1, wherein the selected memory cell comprises a resistivity-switching compound selected from the group consisting of NixOy, NbxOy, TixOy, Hf_xO_y, Al_xO_y, Mg_xO_y, Co_xO_y, Cr_xO_y, V_xO_y, Zn_xO_y, Zr_xO_y, B_xN_y, A1_xN_y.

12. The method of claim 1, wherein the selected memory cell comprises a bipolar metal oxide selected from the group consisting of hafnium oxide (HfO_x), nickel oxide (NiO), and titanium oxide (TiO_x).

19. The memory device of claim 12, wherein the memory cell programming system is configured such that determining electrical characteristics for a programming pulse comprises determining a voltage and a current limit for the programming pulse.

20. The memory device of claim 12, wherein the memory cell programming system is configured such that determining electrical characteristics for a programming pulse comprises determining a voltage and a current limit for the programming pulse when it is determined that the writing of data to the selected memory cell will involve decreasing resistance of the selected memory cell, and determining a voltage for the programming pulse when it is determined that the writing of data to the selected memory cell will involve increasing resistance of the selected memory cell.

13. A memory device, comprising:

an array of memory cells positioned between a plurality of word lines and a plurality of bit lines, wherein the memory cells are multilevel cell resistance memory cells; and

a memory cell program system configured to write data to selected memory cells, wherein the memory controller circuit is configured to perform operations comprising;

receiving data to be written to the memory device;

selecting a memory cell to which at least a portion of the received data is to be written;

obtaining a current resistance state of the selected memory cell;

determining an objective resistance state for representing data to be written to the selected memory cell;

determining whether the writing of data to the selected memory cell will involve increasing or decreasing resistance of the selected memory cell based on the current resistance state and the objective resistance state;

determining electrical characteristics for a programming pulse that will transform the resistance state of the selected memory cell to the objective resistance state based on the objective resistance state and whether the writing of data to the selected memory cell will involve increasing or decreasing resistance of the selected memory cell; and

applying to the selected memory cell a programming pulse having the determined electrical characteristics;

wherein the electrical characteristics of the programming pulse are configured to control both a current and a voltage of the memory cell to maintain substantially constant power dissipation in the selected memory cell while applying the programming pulse to the selected memory cell.

14. The memory device of claim 13, wherein the memory cells comprise a variable resistance material selected from the group consisting of an antifuse dielectric, fuse, diode and antifuse dielectric arranged in a series, a polysilicon memory effect material, a metal oxide or switchable complex metal oxide material, a carbon nanotube material, a graphene switchable resistivity material, a phase change material, a conductive bridge element, an electrolyte switching material, a switchable polymer material, or carbon resistivity switching material, such as amorphous, polycrystalline or microcrystalline carbon or graphite material.

15. The memory device of claim 13, wherein the memory cells comprise a resistivity-switching compound selected from the group consisting of NixOy, NbxOy, TixOy, Hf_xO_y, Al_xO_y, Mg_xO_y, Co_xO_y, Cr_xO_y, V_xO_y, Zn_xO_y, Zr_xO_y, B_xN_y, Al_xN_y.

16. The memory device of claim 13, wherein the memory cells comprise a bipolar metal oxide resistance storage element and a steering element, wherein bipolar metal oxide resistance storage element comprises a metal oxide selected from the group consisting of hafnium oxide (HfO_x), nickel oxide (NiO), and titanium oxide (TiO_x).

17. The memory device of claim 13, wherein the multilevel cell resistance memory cells and the memory cell programming system are configured such that the memory cells are programmed with programming pulses to store four bits of data in four different resistance states.

18. The memory device of claim 13, wherein the multilevel cell resistance memory cells and the memory cell programming system are configured such that the memory cells are programmed with programming pulses to store six bits of data in six different resistance states.

21. The memory device of claim 13, wherein the memory cell programming system is configured to perform operations further comprising determining a duration for a programming pulse based on the objective resistance state and whether the writing of data to the selected memory cell will involve increasing or decreasing resistance of the selected memory cell,

wherein the memory cell programming system is configured such that applying to the selected memory cell a programming pulse having the determined electrical characteristics comprises applying such a programming pulse for the determined duration.

22. The memory device of claim 13, wherein the memory cell programming system is configured such that determining electrical characteristics for a programming pulse comprises accessing a memory coupled to the memory cell programming system to perform a table look up operation using as inputs the objective resistance state and whether the writing of data to the selected memory cell will involve increasing or decreasing resistance of the selected memory cell and obtaining as an output the electrical characteristics.

23. The memory device of claim 13, wherein the memory cell programming system is configured to perform operations further comprising determining whether the current resistance state is within threshold limits of the objective resistance state,

wherein the memory cell programming system is configured such that applying to the selected memory cell a programming pulse having the determined electrical characteristics comprises applying such a programming pulse to the selected memory cell when the current resistance state is not within the threshold limits of the objective resistance state and not applying a programming pulse to the selected memory cell when the current resistance state is within the threshold limits of the objective resistance state.

24. The memory device of claim 13, wherein the memory cell programming system is configured to perform operations further comprising:

determining a resulting resistance state of the selected memory cell after application of the programming pulse;

determining whether the resulting resistance state is within threshold limits of the objective state; and

reapplying to the selected memory cell a programming pulse having the determined electrical characteristics when the resulting resistance state is not within the threshold limits of the objective state.

25. The memory device of claim 13, wherein the memory cell programming system is configured to perform operations further comprising:

determining a resulting resistance state of the selected memory cell after application of the programming pulse;

determining whether the resulting resistance state is within threshold limits of the objective state; and

determining electrical characteristics for a second programming pulse that will transform the resistance state of the selected memory cell to the objective resistance state based on the determined resulting resistance state and the objective resistance state; and

applying to the selected memory cell a second programming pulse having the determined electrical characteristics for a second programming pulse.

26. The memory device of claim 13, wherein the memory cell programming system is configured such that:

determining electrical characteristics for a programming pulse that will transform the resistance state of the selected memory cell to the objective resistance state comprises determining a number of programming pulses and corresponding electrical characteristics for each of the number of programming pulse which when applied in series will transform the resistance state of the selected memory cell to the objective resistance state, and

applying to the selected memory cell a programming pulse having the determined electrical characteristics comprises applying to the selected memory cell the number of programming pulses each having the corresponding electrical characteristics.

27. The memory device of claim 13, wherein the memory cell programming system comprises:

a memory controller circuit;

a bit line controller coupled to the memory controller circuit and configured to select a bit line in response a control signal from the memory controller circuit;

a word line controller coupled to the memory controller circuit and configured to select a word line in response a control signal from the memory controller circuit;

a programming pulse generator circuit coupled to the memory controller circuit and configured to generate a programming pulse having a voltage for writing data to selected memory cells in response a control signal from the memory controller circuit;

a current limiting circuit coupled to the memory controller circuit and configured to limit current flowing through a selected memory cell during a programming pulse in response a control signal from the memory controller circuit; and

a resistance state determining circuit coupled to the memory controller circuit, the bit line controller and the word line controller and configured to determine a resistance state of a selected memory cell,

wherein;

selecting a memory cell to which at least a portion of the received data is to be written comprises activating the bit line and word line controllers to select the memory cell to which the at least a portion of the received data is to be written;

obtaining a current resistance state of the selected memory cell comprises obtaining the current resistance state of the selected memory cell from the resistance state determining circuit; and

applying to the selected memory cell a programming pulse having the determined electrical characteristics comprises activating the pulse generation circuit and the current limiting circuit to apply to the selected memory cell a programming pulse having the determined electrical characteristics.

28. A memory device, comprising:

an array of storage means for storing a plurality of a data bits in the form of a plurality of correlated resistance states;

means for receiving data to be written to the memory device;

means for selecting a storage means to which at least a portion of the received data is to be written;

means for obtaining a current resistance state of the selected storage means;

means for determining an objective resistance state for representing data to be written to the selected storage means;

means for determining whether the writing of data to the selected storage means will involve increasing or decreasing resistance of the selected storage means based on the current resistance state and the objective resistance state;

means for determining electrical characteristics for a programming pulse that will transform the resistance state of the selected storage means to the objective resistance state based on the objective resistance state and whether the writing of data to the selected storage means will involve increasing or decreasing resistance of the selected storage means; and

means for applying to the selected storage means a programming pulse having the determined electrical characteristics;

wherein means for determining electrical characteristics for a programming pulse comprises means for determining a voltage and a current limit for the programming pulse when it is determined that the writing of data to the selected storage means will involve decreasing resistance of the selected storage means, and determining a voltage for the programming pulse when it is determined that the writing of data to the selected storage means will involve increasing resistance of the selected storage means;

wherein the electrical characteristics of the programming pulse are configured to control both a current and a voltage of the memory cell to maintain substantially constant power dissipation in the selected memory cell while applying the programming pulse to the selected memory cell.

29. The memory device of claim 28, wherein the array of storage means comprises multilevel cell resistance memory cells comprising a variable resistance material selected from the group consisting of an antifuse dielectric, fuse, diode and antifuse dielectric arranged in a series, a polysilicon memory effect material, a metal oxide or switchable complex metal oxide material, a carbon nanotube material, a graphene switchable resistivity material, a phase change material, a conductive bridge element, an electrolyte switching material, a switchable polymer material, or carbon resistivity switching material, such as amorphous, polycrystalline or microcrystalline carbon or graphite material.

30. The memory device of claim 28, wherein the array of storage means comprises multilevel cell resistance memory cells comprising a resistivity-switching compound selected from the group consisting of NixOy, NbxOy, TixOy, Hf_xO_y, Al_xO_y, Mg_xO_y , CO_xO_y, Cr_xO_y, V_xO_y, Zn_xO_y, Zr_xO_y, B_xN_y, Al_xN_y.

31. The memory device of claim 28, wherein the array of storage means comprises multilevel cell resistance memory cells comprising a bipolar metal oxide resistance storage element and a steering element, wherein bipolar metal oxide resistance storage element comprises a metal oxide selected from the group consisting of hafnium oxide (HfO_x), nickel oxide (NiO), and titanium oxide (TiO_x).

32. The memory device of claim 28, wherein the storage means comprises means for storing four bits of data in four different resistance states.

33. The memory device of claim 28, wherein the storage means comprises means for storing six bits of data in six different resistance states.

34. The memory device of claim 32, wherein means for determining electrical characteristics for a programming pulse comprises means for determining a voltage and a current limit for the programming pulse.

35. The memory device of claim 28, wherein means for determining electrical characteristics for a programming pulse comprises means for determining a voltage and a current limit for the programming pulse when it is determined that the writing of data to the selected storage means will involve decreasing resistance of the selected storage means, and determining a voltage for the programming pulse when it is determined that the writing of data to the selected storage means will involve increasing resistance of the selected storage means.

36. The memory device of claim 28, further comprising means for determining a duration for a programming pulse based on the objective resistance state and whether the writing of data to the selected storage means will involve increasing or decreasing resistance of the selected storage means,

wherein means for applying to the selected storage means a programming pulse having the determined electrical characteristics comprises means for applying such a programming pulse for the determined duration.

37. The memory device of claim 28, further comprising means for storing a data table of electrical characteristics of programming pulses for each objective resistance state,

wherein means for determining electrical characteristics for a programming pulse comprises means for perform a table look up operation using as inputs the objective resistance state and whether the writing of data to the selected storage means will involve increasing or decreasing resistance of the selected storage means and obtaining as an output the electrical characteristics for the programming pulse.

38. The memory device of claim 28, further comprising means for determining whether the current resistance state is within threshold limits of the objective resistance state,

wherein means for applying to the selected storage means a programming pulse having the determined electrical characteristics comprises means for applying such a programming pulse to the selected storage means when the current resistance state is not within the threshold limits of the objective resistance state and not applying a programming pulse to the selected storage means when the current resistance state is within the threshold limits of the objective resistance state.

39. The memory device of claim 28, further comprising:

means for determining a resulting resistance state of the selected storage means after application of the programming pulse;

means for determining whether the resulting resistance state is within threshold limits of the objective state; and

means for reapplying to the selected storage means a programming pulse having the determined electrical characteristics when the resulting resistance state is not within the threshold limits of the objective state.

40. The memory device of claim 28, further comprising:

means for determining a resulting resistance state of the selected storage means after application of the programming pulse;

means for determining whether the resulting resistance state is within threshold limits of the objective state; and

means for determining electrical characteristics for a second programming pulse that will transform the resistance state of the selected storage means to the objective resistance state based on the determined resulting resistance state and the objective resistance state; and

means for applying to the selected storage means a second programming pulse having the determined electrical characteristics for a second programming pulse.

41. The memory device of claim 28, wherein:

means for determining electrical characteristics for a programming pulse that will transform the resistance state of the selected storage means to the objective resistance state comprises means for determining a number of programming pulses and corresponding electrical characteristics for each of the number of programming pulses which when applied in series will transform the resistance state of the selected storage means to the objective resistance state, and

means for applying to the selected storage means a programming pulse having the determined electrical characteristics comprises means for applying to the selected storage means the number of programming pulses each having the corresponding electrical characteristics.

42. A method of writing data to a multilevel cell resistance memory device, comprising:

receiving data to be written to the memory device;

selecting a memory cell to which at least a portion of the received data is to be written;

determining whether writing the data to the selected memory cell will involve increasing resistance (RESET) or decreasing resistance (SET) of the memory cell;

determining an appropriate programming voltage and current limit for the resistance state to be achieved in writing the data to the selected memory cell and applying a pulse having a first determined set electrical characteristics when it is determined that writing the data to the selected memory cell will involve decreasing resistance (SET) of the memory cell; and

determining an appropriate programming voltage for the resistance state to be achieved in writing the data to the selected memory cell and applying a pulse having a second determined set electrical characteristics when it is determined that writing the data to the selected memory cell will involve increasing resistance (RESET) of the memory cell; and

wherein the first set electrical characteristics of the programming pulse are configured to control both a current and a voltage of the memory cell to maintain substantially constant power dissipation in the selected memory cell while decreasing resistance (SET) of the memory cell.