Packet switching

• US 8,934,344 B2
• Filed: 01/29/2014
• Issued: 01/13/2015
• Est. Priority Date: 06/24/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Memon, Mazhar I., King, Steven R.
• Primary Examiner(s): ELLIOTT IV, BENJAMIN H
• Application Number:
  US14/167,533
• Publication Number:
  US 20140146675A1
• Time in Patent Office: 349 Days
• Field of Search: 370/235, 370/252, 370/352, 370/359, 370/412, 370/419, 710/29, 710/39, 718/100
• US Class Current: 370/235
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/24 Traffic characterised by specific attributes, e.g. priority or QoS
• CPC Class Codes: H04L 47/2433 Allocation of priorities to traffic types
• CPC Class Codes: H04L 47/2475 for supporting traffic characterised by the type of applications
• CPC Class Codes: H04L 47/2483 involving identification of individual flows
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6255 queue load conditions, e.g. longest queue first
• CPC Class Codes: H04L 47/627 policing
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip

Abstract

In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

Claims

1. An apparatus comprising:

an integrated circuit chip that comprises a network interface controller, the integrated circuit chip also comprising switch circuitry to determine, at least in part, an action to be executed involving a packet, determination of the action being based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information, the switch circuitry being to examine, at least in part, the policy information to determine, at least in part, whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information;

if the switch circuitry determines, at least in part, that the previously-established policy has not been established, the switch circuitry is to place the packet in a queue;

after the packet has been placed in the queue, the switch circuitry is to carry out the action after the action has been indicated, at least in part;

the action being selected so as to implement at least one of;

application targeted packet routing to selected virtual machine queues in accordance with packet-flow-based prioritization;

Ethernet header based quality of service prioritization;

application-layer-based load-balancing among the virtual machine queues; and

content-based load balancing among the virtual machine queues.

2. The apparatus of claim 1, wherein:

the packet-flow-based prioritization is packet-flow-based quality of service prioritization.

3. The apparatus of claim 1, wherein:

the application-layer-based load-balancing is implemented so as to balance packet processing load to virtual machines executing applications best suited to process received packets.

4. The apparatus of claim 1, wherein:

the content-based load balancing is implemented so as to balance packet processing load to virtual machines executing applications best suited to process received packets.

5. The apparatus of claim 1, wherein:

the integrated circuit chip also comprises a host processor that comprises a plurality of processor cores.

6. The apparatus of claim 5, wherein:

a host comprises the integrated circuit;

the host comprises the host processor; and

the host processor is to execute at least one control module to establish, at least in part, the previously-established packet processing policy.

7. A method comprising:

determining, at least in part, by switch circuitry, an action to be executed involving a packet, the determining being based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information, the switch circuitry being to examine, at least in part, the policy information to determine, at least in part, whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information;

an integrated circuit chip comprising the switch circuitry and a network interface controller;

if the switch circuitry determines, at least in part, that the previously-established policy has not been established, the switch circuitry is to place the packet in a queue;

after the packet has been placed in the queue, the switch circuitry is to carry out the action after the action has been indicated, at least in part;

the action being selected so as to implement at least one of;

application targeted packet routing to selected virtual machine queues in accordance with packet-flow-based prioritization;

Ethernet header based quality of service prioritization;

application-layer-based load-balancing among the virtual machine queues; and

content-based load balancing among the virtual machine queues.

8. The method of claim 7, wherein:

the packet-flow-based prioritization is packet-flow-based quality of service prioritization.

9. The method of claim 7, wherein:

the application-layer-based load-balancing is implemented so as to balance packet processing load to virtual machines executing applications best suited to process received packets.

10. The method of claim 7, wherein:

the content-based load balancing is implemented so as to balance packet processing load to virtual machines executing applications best suited to process received packets.

11. The method of claim 7, wherein:

the integrated circuit chip also comprises a host processor that comprises a plurality of processor cores.

12. The method of claim 11, wherein:

a host comprises the integrated circuit;

the host comprises the host processor; and

the host processor is to execute at least one control module to establish, at least in part, the previously-established packet processing policy.

13. Non-transitory machine-readable memory storing one or more instructions that when executed by a machine result in execution of operations comprising:

determining, at least in part, by switch circuitry, an action to be executed involving a packet, the determining being based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information, the switch circuitry being to examine, at least in part, the policy information to determine, at least in part, whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information;

an integrated circuit chip comprising the switch circuitry and a network interface controller;

if the switch circuitry determines, at least in part, that the previously-established policy has not been established, the switch circuitry is to place the packet in a queue;

after the packet has been placed in the queue, the switch circuitry is to carry out the action after the action has been indicated, at least in part;

the action being selected so as to implement at least one of;

application targeted packet routing to selected virtual machine queues in accordance with packet-flow-based prioritization;

Ethernet header based quality of service prioritization;

application-layer-based load-balancing among the virtual machine queues; and

content-based load balancing among the virtual machine queues.

14. The memory of claim 13, wherein:

the packet-flow-based prioritization is packet-flow-based quality of service prioritization.

15. The memory of claim 13, wherein:

the application-layer-based load-balancing is implemented so as to balance packet processing load to virtual machines executing applications best suited to process received packets.

16. The memory of claim 13, wherein:

the content-based load balancing is implemented so as to balance packet processing load to virtual machines executing applications best suited to process received packets.

17. The memory of claim 13, wherein:

the integrated circuit chip also comprises a host processor that comprises a plurality of processor cores.

18. The memory of claim 17, wherein:

a host comprises the integrated circuit;

the host comprises the host processor; and

the host processor is to execute at least one control module to establish, at least in part, the previously-established packet processing policy.