Network communications circuit, system and method

• US 8,935,450 B2
• Filed: 09/16/2011
• Issued: 01/13/2015
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Nierop, Pieter Gustaaf, de Haas, Clemens Gerhardus Johannes, Evers, Rainer, Klosters, Franciscus Johannes
• Primary Examiner(s): MISIURA, BRIAN THOMAS
• Application Number:
  US13/234,798
• Publication Number:
  US 20130073761A1
• Time in Patent Office: 1,215 Days
• Field of Search: 710/9, 710/110
• US Class Current: 710/110
• CPC Class Codes: H04L 12/40045 Details regarding the feeding of energy to the node from the bus
• CPC Class Codes: H04L 2012/40234 Local Interconnect Network LIN

Abstract

Various exemplary aspects are directed to apparatuses and methods involving switches communicatively-coupled on a bus where one or more of the switches operate to block signals from passing through the switch in a first mode, and to pass signals through the switch in a second mode. A logic circuit is responsive to addressing information received in the first mode, by storing and configuring the apparatus with the address information. The logic circuit ignores address information received in the second mode (e.g., does not reconfigure the apparatus with address information received in the second mode).

Claims

1. An apparatus comprising a master circuit and a plurality of slave circuits communicatively coupled in a cascaded arrangement via a current-carrying bus, each of the slave circuits including circuitry having a switch that includes a transistor having current passing terminals and that is configured and arranged to, in response to a control signal received over the bus, interrupt and thereby block current and data conveyed on the current-carrying bus from passing to another one of the slave circuits that is immediately adjacent in the cascaded arrangement, wherein the circuitry is configured and arranged to control the current through the terminals based on a bias signal operating in the circuitry and affecting a current passing operation of the transistor, wherein the switch includes a gate and a source and an impedance circuit is connected between the gate and the source.

2. The apparatus of claim 1, wherein each of the slave circuits is configured and arranged to, in response to receiving an address assignment signal from the master circuit, store address information and close the switch to pass current from the master circuit to another one of the slave circuits.

3. The apparatus of claim 2, wherein the master circuit is configured and arranged to send the control signal and, after sending the control signal, to send successive address assignment signals for assigning an address to successive ones of the slave circuits, each slave circuit respectively configured and arranged to respond to the address assignment signals by, after storing address information and closing the switch in response to a first-received one of the address assignment signals, ignoring subsequent address-assignment signals.

4. The apparatus of claim 3, wherein the slave circuit includes a microcontroller configured and arranged to respond to the address assignment signals by, after storing the address information, generating a signal to close the switch in response to a first-received one of the address assignment signals, and ignoring subsequent address-assignment signals.

5. The apparatus of claim 2, wherein the slave circuits are configured and arranged to, in response to receiving the address assignment signal for which the address information is stored, communicate an acknowledgement signal to the master circuit, the master circuit being configured and arranged to respond to the acknowledgement signal by communicating another address assignment signal on the bus for another one of the slave circuits on the bus.

6. An apparatus comprising:

circuitry having a switch with terminals including a gate and a source and a drain;

a control circuit connected to the gate and configured and arranged to apply a bias to the gate to control a conductance state of the switch by, in response to a control signal presented at the source,

in a first mode, controlling the switch in an open state to block signals from passing through the switch, and

in a second mode, controlling the switch in a closed state to pass signals through the switch; and

a logic circuit configured and arranged to respond to address information received in a signal presented at the source by, in the first mode, storing the address information to configure the apparatus with the address and, in the second mode, ignoring address information in signals presented at the source, wherein the circuitry is configured and arranged to control the current through the terminals based on a bias signal operating in the circuitry and affecting a current passing operation of the switch, wherein an impedance circuit is connected between the gate and the source.

7. The apparatus of claim 6, further including a microcontroller configured and arranged to respond to a configuration signal received at the switch by generating and providing the control signal, the control circuit being configured and arranged to control the switch in the open state or the closed state based on the control signal generated by the microcontroller.

8. The apparatus of claim 7, wherein the microcontroller includes the logic circuit.

9. The apparatus of claim 7, wherein the apparatus is part of an addressable slave circuit, and the microcontroller is configured and arranged to generate and provide the control signal to

operate the switch in the first mode to assign an address to the slave circuit,

operate the switch in the second mode after an address has been assigned to the slave circuit, and

operate the switch in the first mode to re-assign an address to the slave circuit, after an address has been assigned to the slave circuit, the logic circuit being responsive to new address information received at the switch by storing the new address information for the slave circuit.

10. The apparatus of claim 7, wherein the microcontroller is configured and arranged to respond to the control signal in the first mode by, in response to receiving address data, switching the control circuit to the second mode.

11. The apparatus of claim 7, wherein the microcontroller is configured and arranged to

operate the control circuit in the first mode until address data is received via a communications bus coupled to the switch, and

in response to receiving the address data, use the address data to identify communications on the bus as being communications for the microcontroller, and switching to the second mode.

12. An apparatus comprising:

a switch having a gate, a source and a drain;

a control circuit connected to the gate and configured and arranged to apply a bias to the gate to control a conductance state of the switch by, in response to a control signal presented at the source,

in a first mode, controlling the switch in an open state to block signals from passing through the switch, and

in a second mode, controlling the switch in a closed state to pass signals through the switch;

a logic circuit configured and arranged to respond to address information received in a signal presented at the source by, in the first mode, storing the address information to configure the apparatus with the address and, in the second mode, ignoring address information in signals presented at the source; and

an impedance circuit connected between the gate and the source, wherein the control circuit is connected to the gate and the impedance circuit, and the control circuit is configured and arranged to

control the switch in the open state by flowing a bias current of a first polarity through the impedance circuit, and

control the switch in the closed state by flowing a bias current of opposite polarity through the impedance circuit.

13. The apparatus of claim 12 wherein the control circuit includes a switch and a resistor connected between the switch and the gate, the switch being configured and arranged to connect the resistor to a ground node for flowing the bias current at a first polarity, and to connect the resistor to a voltage supply to flowing the bias current at a second polarity that is opposite the first polarity.

14. The apparatus of claim 12, wherein the impedance circuit includes two sets of diodes arranged in anti-parallel between the gate and source.

15. The apparatus of claim 12, wherein the impedance circuit includes two sets of diodes respectively configured and arranged to pass current in opposite directions between the gate and source.

16. A communication apparatus comprising:

a master circuit that includes a transistor having current passing terminals, at a master node, configured and arranged to communicate a configuration signal and an address signal on a communications bus; and

a plurality of slave circuits at slave nodes on the bus, each slave circuit having a switch that couples the slave circuit to an immediately adjacent slave circuit on the bus, and each slave circuit being configured and arranged to respond to the configuration signal by,

in a first mode, controlling the switch in an open state to block the address signal from passing to the immediately adjacent slave circuit on the bus, storing address information from the address signal, and switching to a second mode after storing the address information, and

in the second mode, controlling the switch in a closed state to pass the address signal to the immediately adjacent slave circuit on the bus, wherein the circuitry is configured and arranged to control the current through the terminals based on a bias signal operating in the circuitry and affecting a current passing operation of the transistor, wherein the switch includes a gate and a source and an impedance circuit connected between the gate and the source.

17. The communication apparatus of claim 16, wherein

the slave circuits are configured and arranged to, in response to storing the address information, communicate an acknowledgement signal to the master circuit, and

the master circuit is configured and arranged to respond to the acknowledgement signal by communicating another address signal on the bus for another one of the slave circuits on the bus.

18. A method for assigning addresses to a plurality of slave circuits connected to each other and to a master circuit in a cascaded arrangement on a bus that includes a transistor having current passing terminals, the method comprising:

communicating, from the master circuit, a first signal;

at each slave circuit receiving the first signal, opening a switch to block further communications from passing from the master circuit, through the slave circuit and to another immediately adjacent slave circuit on the bus;

communicating, from the master circuit, a second signal including address assignment data; and

at one of the slave circuits, in response to receiving the address assignment data, storing data indicative of an address in the address assignment data, and closing a switch to pass communications from the master circuit to an immediately adjacent slave circuit on the bus, wherein the circuitry is configured and arranged to control the current through the terminals based on a bias signal operating in the circuitry and affecting a current passing operation of the transistor, wherein the switch includes a gate and a source and an impedance circuit connected between the gate and the source.

19. The method of claim 18, further including

communicating, from the master circuit, a third signal including address assignment data for another one of the slave circuits, and

at the other one of the slave circuits, in response to receiving the address assignment data in the third signal, storing data indicative of an address in the address assignment data, and closing a switch to pass communications from the master circuit to an immediately adjacent slave circuit on the bus.

20. The method of claim 18, wherein opening a switch and closing a switch respectively include operating a microcontroller to generate control signals to control the switch to respectively operate in an open state and in a closed state, and wherein storing data includes operating the microcontroller to process the address assignment data and store address assignment information therein.