Semiconductor device, radio communication terminal using same, and clock frequency control method

• US 8,935,553 B2
• Filed: 07/04/2012
• Issued: 01/13/2015
• Est. Priority Date: 07/06/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Mobile Corporation (Renesas Electronics Corporation)
• Inventors: Wakahara, Kohei, Fujigaya, Masaki, Irita, Takahiro, Matsuyama, Tsugio
• Primary Examiner(s): WANG, ALBERT C
• Application Number:
  US13/541,731
• Publication Number:
  US 20130009687A1
• Time in Patent Office: 923 Days
• Field of Search: 713/322
• US Class Current: 713/322
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.

Claims

1. A semiconductor device comprising:

a clock generation circuit that changes a frequency of an output clock signal according to a control signal;

an arithmetic circuit that operates according to the clock signal;

a storage circuit that is activated according to access from the arithmetic circuit;

a memory access detection unit that detects a number of accesses from the arithmetic circuit to the storage circuit, and when the number of accesses increases, outputs a request signal to lower the frequency of the clock signal; and

a clock control circuit that generates the control signal for lowering the frequency of the clock signal according to the request signal,

wherein the memory access detection unit comprises a second comparator that compares a variation of an index number calculated from the number of accesses with a second reference value, and when the variation of the index number exceeds the second reference value, outputs a second request signal as the request signal.

2. The semiconductor device according to claim 1,

wherein the memory access detection unit comprises a first comparator that compares an index number calculated from the number of accesses with a first reference value, and when the index number exceeds the first reference value, outputs a first request signal as the request signal.

3. The semiconductor device according to claim 2,

wherein the clock control circuit comprises a first clock adjustment unit that generates a first control signal as the control signal according to the first request signal, the first control signal being used to decrease a number of clocks output in a predetermined period in a stepwise manner.

4. The semiconductor device according to claim 3,

wherein the first control signal is used to decrease the number of clocks output in the predetermined period by one at a time.

5. The semiconductor device according to claim 2, further comprising:

first and second storage circuits as the storage circuit,

wherein the index number is determined based on a product of a number of accesses to the first storage circuit and a weight defined for the first storage circuit, and a product of a number of accesses to the second storage circuit and a weight defined for the first storage circuit.

6. The semiconductor device according to claim 5, wherein

each of the first and second storage circuits includes a plurality of blocks, and

the memory access detection unit detects a number of accesses to each of the plurality of blocks.

7. The semiconductor device according to claim 6,

wherein the weight is a value determined according to a current value necessary for one access to each of the plurality of blocks.

8. The semiconductor device according to claim 1,

wherein the clock control circuit comprises a second clock adjustment unit that generates a second control signal as the control signal according to the second request signal, the second control signal being used to decrease a number of clocks output in a predetermined period to a lower limit value.

9. The semiconductor device according to claim 8,

wherein the lower limit value can be defined.

10. The semiconductor device according to claim 1,

wherein a number of the arithmetic circuit is two or more.

11. The semiconductor device according to claim 1,

wherein the storage circuit is a cache memory.

12. A radio communication terminal comprising a semiconductor device according to claim 1.

13. A semiconductor device, comprising:

a clock generation circuit that changes a frequency of an output clock signal according to a control signal;

an arithmetic circuit that operates according to the clock signal;

a storage circuit that is activated according to access from the arithmetic circuit;

a memory access detection unit that detects a number of accesses from the arithmetic circuit to the storage circuit, and when the number of accesses increases, outputs a request signal to lower the frequency of the clock signal; and

a clock control circuit that generates the control signal for lowering the frequency of the clock signal according to the request signal,

wherein the memory access detection unit comprises;

a first comparator that compares an index number calculated from the number of accesses with a first reference value, and when the index number exceeds the first reference value, outputs a first request signal as the request signal; and

a second comparator that compares a variation of the index number with a second reference value, and when the variation of the index number exceeds the second reference value, outputs a second request signal as the request signal, and

wherein the clock control circuit comprises;

a first clock adjustment unit that generates a first control signal as the control signal according to the first request signal, the first control signal being used to decrease a number of clocks output in a predetermined period in a stepwise manner; and

a second clock adjustment unit that generates a second control signal as the control signal according to the second request signal, the second control signal being used to decrease the number of clocks output in the predetermined period to a lower limit value.

14. The semiconductor device according to claim 13,

wherein when the first and second request signals are simultaneously output from the memory access detection unit, the clock control circuit gives a higher priority to the second request signal.

15. A clock frequency control method for a clock signal supplied to a semiconductor device comprising an arithmetic circuit that operates according to the clock signal and a storage circuit that is activated according to access from the arithmetic circuit, the clock frequency control method comprising:

detecting a number of accesses from the arithmetic circuit to the storage circuit;

calculating an index number based on the number of accesses;

comparing a variation of the index number with a first reference value; and

lowering a frequency of the clock signal when the variation of the index number exceeds the first reference value due to an increase in the number of accesses.

16. The clock frequency control method according to claim 15, further comprising:

comparing the index number with a second reference value, and

lowering the frequency of the clock signal when the index number exceeds the second reference value due to an increase in the number of accesses.

17. The clock frequency control method according to claim 16,

wherein when the frequency of the clock signal is lowered, a number of clocks output in a predetermined period is decreased in a stepwise manner.

18. The clock frequency control method according to claim 17,

wherein the number of clocks output in the predetermined period is decreased by one at a time.

19. The clock frequency control method according to claim 15,

wherein when the frequency of the clock signal is lowered, a number of clocks output in a predetermined period is decreased to a lower limit value.

20. The clock frequency control method according to claim 19,

wherein after the number of clocks output in the predetermined period is decreased to the lower limit value, if the variation of the index number is smaller than or equal to the first reference value, the number of clocks output in the predetermined period is increased in a stepwise manner.

21. The clock frequency control method according to claim 20,

wherein the number of clocks output in the predetermined period is increased by one at a time.