Transport network

• US 8,935,640 B2
• Filed: 04/17/2013
• Issued: 01/13/2015
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Caldwell, Andrew, Teig, Steven, Hutchings, Brad
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US13/864,507
• Publication Number:
  US 20140109028A1
• Time in Patent Office: 636 Days
• Field of Search: 716103-108, 716/116
• US Class Current: 716/103
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing

Abstract

Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.

Claims

1. An integrated circuit (IC) comprising:

an arrangement of circuits comprising a plurality of configurable circuits for configurably performing a plurality of operations;

a plurality of signal paths for monitoring signals generated by the plurality of configurable circuits and for outputting the monitored signals; and

a transport network for transporting the monitored signals outputted by the plurality of signal paths to a set of destination circuits, wherein the transport network is divided into a plurality of sections, each section of at least some of the plurality of sections for transporting a selected data bit to a next section of the transport network, wherein the selected data bit is selected from (i) a data bit transported from a previous section of the transport network and (ii) a monitored signal outputted by one of the plurality of signal paths.

2. The IC of claim 1, wherein a last section of the transport network is for transporting a selected data bit to the set of destination circuits, wherein the selected data bit is selected from (i) a data bit transported from a previous section of the transport network and (ii) a monitored signal outputted by one of the plurality of signal paths.

3. The IC of claim 1, wherein a beginning section of the transport network is for transporting a monitored signal outputted by one of the plurality of signal paths to a next section of the transport network.

4. The IC of claim 1, wherein two consecutive sections of the transport network are interconnected by a set of storage elements.

5. The IC of claim 1, wherein the each section of the at least some of the plurality of sections comprises a set of storage elements for delaying a monitored data bit outputted by one of the plurality of signal paths when the section is transporting the data bit transported from the previous section.

6. The IC of claim 1, wherein the plurality of signal paths monitors signals generated by the plurality of configurable circuits by sampling once every clock cycle.

7. The IC of claim 6, wherein each clock cycle is divided into a plurality of sub-cycles, wherein each data bit transported by the transport network traverses one section of the transport network in one sub-cycle.

8. The IC of claim 1, wherein the set of destination circuits comprises a trace buffer.

9. The IC of claim 1, wherein the set of destination circuits comprises a trigger circuit.

10. The IC of claim 9, wherein the set of destination circuits further comprises a deskew circuit.

11. An electronic device comprising:

an integrated circuit (IC) comprising;

an arrangement of circuits comprising a plurality of configurable circuits for configurably performing a plurality of operations;

a plurality of signal paths for monitoring signals generated by the plurality of configurable circuits and for outputting the monitored signals; and

a transport network for transporting the monitored signals outputted by the plurality of signal paths to a set of destination circuits, wherein the transport network is divided into a plurality of sections, each section of at least some of the plurality of sections for transporting a selected data bit to a next section of the transport network, wherein the selected data bit is selected from (i) a data bit transported from a previous section of the transport network and (ii) a monitored signal outputted by one of the plurality of signal paths; and

a memory device for storing configuration data for configuring the plurality of configurable circuits in the IC.

12. The electronic device of claim 11, wherein a last section of the transport network is for transporting a selected data bit to the set of destination circuits, wherein the selected data bit is selected from (i) a data bit transported from a previous section of the transport network and (ii) a monitored signal outputted by one of the plurality of signal paths.

13. The electronic device of claim 11, wherein a beginning section of the transport network is for transporting a monitored signal outputted by one of the plurality of signal paths to a next section of the transport network.

14. The electronic device of claim 11, wherein two consecutive sections of the transport network are interconnected by a set of storage elements.

15. The electronic device of claim 11, wherein the each section of the at least some of the plurality of sections comprises a set of storage elements for delaying a monitored data bit outputted by one of the plurality of signal paths when the section is transporting the data bit transported from the previous section.

16. The electronic device of claim 11, wherein the plurality of signal paths monitors signals generated by the plurality of configurable circuits by sampling once every clock cycle.

17. The electronic device of claim 16, wherein each clock cycle is divided into a plurality of sub-cycles, wherein each data bit transported by the transport network traverses one section of the transport network in one sub-cycle.

18. The electronic device of claim 11, wherein the set of destination circuits comprises a trace buffer.

19. The electronic device of claim 11, wherein the set of destination circuits comprises a trigger circuit.

20. The electronic device of claim 19, wherein the set of destination circuits further comprises a deskew circuit.