Decision modules

• US 8,935,647 B2
• Filed: 08/31/2013
• Issued: 01/13/2015
• Est. Priority Date: 05/24/2008
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Caldwell, Andrew, Teig, Steven
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US14/016,057
• Publication Number:
  US 20140007027A1
• Time in Patent Office: 500 Days
• Field of Search: 716/122, 716/129, 716/130, 716/104, 703/16
• US Class Current: 716/122
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information.

The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.

Claims

1. An automated method of defining a physical design for an integrated circuit (IC), the method comprising:

at a computer, receiving an abstract circuit representation of the IC design comprising a plurality of segments, wherein a particular segment of the abstract circuit representation comprises a decision module that comprises a plurality of alternative implementations for performing functionality of the particular segment;

selecting a particular alternative implementation from the plurality of alternative implementations of the decision module; and

at a computer, placing the particular segment based on the selected particular alternative implementation in the physical design for the IC.

2. The method of claim 1 further comprising determining a placement cost for at least one alternative implementation in the plurality of alternative implementations.

3. The method of claim 2 further comprising identifying placements of other segments that are related to the particular segment, wherein determining the placement cost of the at least one alternative implementation is further based on the placements of the related segments.

4. The method of claim 2, wherein selecting the particular alternative implementation comprises identifying a first alternative implementation of the plurality of alternative implementations with a placement cost lower than a threshold value.

5. The method of claim 2, wherein selecting the particular alternative implementation comprises identifying an alternative implementation with the lowest placement cost among the plurality of alternative implementations.

6. The method of claim 2, wherein the placement cost for an alternative implementation is based on at least one of a circuit area and a signal delay.

7. The method of claim 2 further comprising determining a routing cost for at least one alternative implementation of the plurality of alternative implementations, wherein selecting the particular alternative implementation is further based on the determined routing costs.

8. The method of claim 1, wherein selecting the particular alternative implementation comprises determining whether the particular alternative implementation satisfies a set of design constraints.

9. The method of claim 8, wherein the set of design constraints comprises congestion goals.

10. A non-transitory machine readable medium for storing a program for defining a physical design for an integrated circuit (IC), the program comprising sets of instructions for:

receiving, at a computer, a netlist of the IC design comprising a plurality of components, wherein a particular component of the netlist comprises a decision module for providing a plurality of alternative implementations for the particular component;

selecting a particular alternative implementation from the plurality of alternative implementations of the decision module; and

placing the particular component in the physical design of the IC based on the selected particular alternative implementation.

11. The non-transitory machine readable medium of claim 10 further comprising a set of instructions for determining a placement cost for at least one alternative implementation in the plurality of alternative implementations.

12. The non-transitory machine readable medium of claim 11, wherein the program further comprises a set of instructions for identifying placements of other components that are related to the particular component, wherein determining the placement cost of the at least one alternative implementation is further based on the placements of the related segments.

13. The non-transitory machine readable medium of claim 11, wherein the set of instructions for selecting the particular alternative implementation comprises a set of instructions for identifying a first alternative implementation of the plurality of alternative implementations with a placement cost lower than a threshold value.

14. The non-transitory machine readable medium of claim 11, wherein the set of instructions for selecting the particular alternative implementation comprises a set of instructions for identifying an alternative implementation with the lowest placement cost among the plurality of alternative implementations.

15. The non-transitory machine readable medium of claim 10, wherein the set of instructions for selecting the particular alternative implementation comprises a set of instructions for determining whether the particular alternative implementation satisfies a set of design constraints.

16. The non-transitory machine readable medium of claim 10, wherein the program further comprises a set of instructions for determining a routing cost for at least one alternative implementation of the plurality of alternative implementations, wherein the set of instructions for selecting the particular alternative implementation is further based on the determined routing costs.

17. An automated method of defining a physical design for an integrated circuit (IC), the method comprising:

receiving, at a computer, an abstract circuit representation of the IC design comprising a plurality of segments, wherein a particular segment of the abstract circuit representation comprises a decision module that provides a plurality of alternative synthesis solutions for performing functionality of the particular segment;

identifying a set of physical design constraints for placement of the particular segment;

eliminating synthesis solutions of the plurality of alternative synthesis solutions of the decision module that do not satisfy the identified set of physical design constraints; and

identifying, at the computer, a placement solution for the particular segment based on the remaining synthesis solutions.

18. The method of claim 17, wherein identifying the placement solution comprises determining a placement cost for at least one synthesis solution in the remaining synthesis solutions.

19. The method of claim 18, wherein the placement cost for an alternative synthesis solution is based on at least one of a circuit area, wiring congestion, and a signal delay.

20. The method of claim 18, wherein identifying the placement solution comprises identifying one synthesis solution from the remaining synthesis solutions with a placement cost lower than a threshold value.