Conductivity improvements for III-V semiconductor devices

• US 8,936,976 B2
• Filed: 12/23/2009
• Issued: 01/20/2015
• Est. Priority Date: 12/23/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Radosavljevic, Marko, Majhi, Prashant, Kavalieros, Jack T., Goel, Niti, Tsai, Wilman, Mukherjee, Niloy, Lee, Yong Ju, Dewey, Gilbert, Rachmady, Willy
• Primary Examiner(s): Matthews, Colleen A
• Assistant Examiner(s): SNOW, COLLEEN ERIN
• Application Number:
  US12/646,711
• Publication Number:
  US 20110147798A1
• Time in Patent Office: 1,854 Days
• Field of Search: 257/194, 257/E29.246, 257/E21.403, 438/172, 438/249, 438/365, 438/368, 438/371, 438/392, 438/558
• US Class Current: 438/172
• CPC Class Codes: H01L 21/2256 through the applied layer
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

Claims

1. A method of forming a transistor, comprising:

forming a III-V semiconductor stack by epitaxially forming a first III-V layer directly on a III-V channel layer, said III-V channel layer epitaxially formed directly on a III-V buffer layer;

etching said first III-V layer where said transistor'"'"'s gate electrode is to be placed, said etching creating a void within said first III-V layer, said III-V buffer layer not acting as an etch stop for said etch;

epitaxially forming a barrier layer in said void that fills said void;

forming a gate electrode over said barrier layer wherein an end of said gate electrode that is closest to said III-V channel layer extends into said barrier layer; and

,

forming source and drain electrodes over said first III-V layer.

2. The method of claim 1 wherein said first III-V layer is Indium Gallium Arsenide.

3. The method of claim 2 wherein said III-V channel layer is Indium Gallium Arsenide.

4. The method of claim 3 wherein said first III-V layer has a higher composition percentage of Indium than said III-V channel layer.

5. The method of claim 1 further comprising forming an etch stop layer within said void before said forming of said gate electrode.

6. The method of claim 5 further comprising etching through said etch stop layer and into said III-V barrier layer before said forming of said gate electrode, said gate electrode being a recessed gate electrode after said forming of said gate electrode.

7. A method, comprising:

forming a first layer composed of Si and/or Ge on an undoped III-V material;

forming a second metal layer on the first layer, said second metal layer composed of any of the following;

Ni, Ti, Al, Hf, Zr and W;

annealing said first layer, said second metal layer and said III-V material to;

i) provide respective Si and/or Ge dopants into said III-V material;

ii) provide metal of said second layer into said first layer;

removing said second layer; and

,

forming an electrode on said first layer.

8. The method of claim 7 wherein said electrode is a source electrode.

9. The method of claim 7 wherein said electrode is a drain electrode.

10. The method of claim 7 wherein said forming a first layer includes forming said first layer by any of:

CVD, MOCVD, MBE or ALE.

11. The method of claim 10 wherein said forming a second layer includes forming said second layer by any of:

ALE, PVD, sputtering, evaporation.

12. The method of claim 7 wherein said forming a second layer includes forming said second layer by any of:

ALE, PVD, sputtering, evaporation.

13. A method of forming a transistor, comprising:

forming a layer of material composed of a Group IV element and a Group VI element on an exposed undoped region of a channel layer, said channel layer composed of a III-V material;

doping said exposed region of said channel layer by driving said Group IV element and said Group VI element into said exposed region of said channel layer with any of the following;

spike anneal;

flash anneal;

laser anneal; and

,

forming an electrode over said doped channel layer region.

14. The method of claim 13 wherein said layer of material is a monolayer.

15. The method of claim 13 wherein said layer of material is formed by any of:

plasma vapor deposition;

molecular beam epitaxy;

chemical vapor deposition;

molecular implantation;

molecular layer deposition;

infusion doping;

plasma doping.

16. The method of claim 13 wherein said layer of material is spin on glass (SOG) and said method further comprises prior to said driving:

driving said Group IV and VI elements from the SOG to the surface of the exposed region of the channel layer; and

,

removing said SOG layer with a wet etch.

17. The method of claim 13 wherein said Group VI element occupies a Group V site of said exposed region of said channel layer.

18. The method of claim 13 wherein said doped exposed channel layer region has a dopant depth of less than 10 nm and a dopant concentration of at least 1e20/cm3.

19. A method of forming a transistor, comprising:

forming a layer of material composed of a Group IV element on an exposed undoped region of a channel layer, said channel layer composed of a III-V material;

doping said exposed region of said channel layer by driving said Group IV element into said exposed region of said channel layer in an environment that promotes said Group IV element'"'"'s occupation of a Group III lattice site of said channel layer and not a Group V lattice site of said channel layer, wherein said environment includes overpressure of a Group V element, said driving accomplished with any of the following;

spike anneal;

flash anneal;

laser anneal; and

,

forming an electrode over said doped channel layer region.

20. A method of forming a transistor, comprising:

forming a layer of material composed of a Group IV element on an exposed undoped region of a channel layer, said channel layer composed of a III-V material;

doping said exposed region of said channel layer by driving said Group IV element into said exposed region of said channel layer in an environment that promotes said Group IV element'"'"'s occupation of a Group III lattice site of said channel layer and not a Group V lattice site of said channel layer, wherein said environment includes overpressure of a Group V element and wherein said Group V element is selected from the group consisting of;

As;

Sb;

said driving accomplished with any of the following;

spike anneal;

flash anneal;

laser anneal; and

,

forming an electrode over said doped channel layer region.