Methods related to power semiconductor devices with thick bottom oxide layers

• US 8,936,985 B2
• Filed: 03/12/2012
• Issued: 01/20/2015
• Est. Priority Date: 05/20/2003
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Challa, Ashok, Elbanhawy, Alan, Probst, Dean E., Sapp, Steven P., Wilson, Peter H., Sani, Babak S., Losee, Becky, Herrick, Robert, Murphy, James J., Madson, Gordon K., Marchant, Bruce D., Kocon, Christopher B., Woolsey, Debra S.
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US13/418,128
• Publication Number:
  US 20120220091A1
• Time in Patent Office: 1,044 Days
• Field of Search: 438/270
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 : with a recessed gate
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/00 : Conversion of dc power input into dc power output
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a drift region of a first conductivity type;

forming a well region above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench;

forming a charge control trench extending through a portion of the well region and deeper into the drift region than the active trench, the charge control trench being aligned parallel to the active trench and being laterally separated from the active trench by a mesa region, the portion of the well region being in contact with the charge control trench and excluding any source region;

forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench;

forming an electrode in the active trench; and

forming a source region, having the first conductivity type, in the well region.

2. The method of claim 1, wherein the forming the oxide further includes:

forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that substantially fills the active trench and covers at least a portion of a top surface of a semiconductor substrate; and

etching at least a first portion of the oxide film off a top surface of the semiconductor substrate; and

etching at least a second portion of the oxide film from inside the trench leaving a substantially flat layer of the oxide along the bottom of the active trench.

3. The method of claim 1, wherein the oxide along the bottom of the bottom of the active trench and the oxide along the first sidewall of the active trench are formed using a temperature treatment to densify at least a portion of the oxide.

4. The method of claim 1, wherein the forming the oxide further includes:

depositing the oxide by a directional Tetraethoxysilate (TEOS) process that forms a thicker film of the oxide on horizontal surfaces including the bottom of the active trench than vertical surfaces including the first sidewall of the active trench; and

isotropically etching the oxide until all of the oxide on the first sidewall of the active trench is removed leaving the oxide along the bottom of the active trench having a target thickness.

5. The method of claim 1, wherein the oxide along the bottom of the bottom of the active trench and the oxide along the first sidewall of the active trench are formed using a dry top oxide etch followed by a wet buffered oxide etch.

6. The method of claim 1, wherein the oxide along the bottom of the bottom of the active trench and the oxide along the first sidewall of the active trench are formed using a dry top oxide etch, the dry top oxide etch includes a fog etch process that etches a portion of the oxide near a top edge of the active trench at an accelerated rate as compared to a portion of the oxide near the bottom of the active trench.

7. The method of claim 1, wherein the forming the oxide along the bottom of the active trench and the oxide along the first sidewall of the active trench includes depositing using a high density plasma deposition process,

the method further comprising:

removing at least a portion of the oxide from the first sidewall of the active trench by a wet etch process such that a profile of the active trench slopes away from the active trench near a top of the active trench.

8. A method, comprising:

forming a trench in a semiconductor substrate;

forming a layer of pad oxide on the semiconductor substrate;

depositing a layer of silicon nitride on the pad oxide;

performing an anisotropic etch to remove silicon nitride from at least a portion of a bottom of the trench and leaving at least a portion of the layer of silicon nitride on a sidewall of the trench;

depositing, using a sub-atmospheric chemical vapor deposition process, an oxide on the portion of the bottom of the trench, the pad oxide, the silicon nitride, and the oxide deposited using the sub-atmospheric chemical vapor deposition process collectively defining at least a portion of a sandwich layer of oxide-nitride-oxide;

removing, using an etch process, the sandwich layer of oxide-nitride-oxide from the sidewall of the trench;

forming a source region adjacent the sidewall of the trench; and

forming a charge control trench laterally spaced from the trench by a mesa region, the charge control trench being aligned parallel to the trench.

9. A method, comprising:

forming a trench in a semiconductor substrate;

forming a layer of pad oxide on the semiconductor substrate including on a sidewall of the trench and on a bottom of the trench;

forming a layer of nitride on top of the pad oxide;

removing a first portion of the layer of nitride from the bottom of the trench and leaving a second portion of the layer of nitride adjacent to the pad oxide on a sidewall of the trench;

removing a portion of the pad oxide exposing a surface of the bottom of the trench;

performing an anisotropic etch of the exposed surface of the bottom of the trench to form a lower trench portion;

forming a layer of oxide in the lower trench portion;

forming at least two electrodes in the trench; and

forming a charge control trench laterally spaced from the trench by a mesa region, the charge control trench being aligned parallel to the trench.

10. A method of manufacturing a semiconductor device, comprising:

forming a drift region of a first conductivity type;

forming a well region above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench;

forming a charge control trench extending through a portion of the well region and deeper into the drift region than the active trench, the charge control trench being aligned parallel to the active trench and being laterally separated from the active trench by a mesa region, the portion of the well region being in contact with the charge control trench and excluding any source region;

forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench the forming the oxide includes removing a pad oxide from a plurality of horizontal surfaces including a portion of the bottom of the trench;

forming an electrode in the active trench; and

forming the first source region, having the first conductivity type, in the well region.

11. A method of manufacturing a semiconductor device, comprising:

forming a drift region of a first conductivity type;

forming a well region above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench;

forming a charge control trench extending through a portion of the well region and deeper into the drift region than the active trench, the charge control trench being aligned parallel to the active trench and being laterally separated from the active trench by a mesa region, the portion of the well region being in contact with the charge control trench and excluding any source region;

forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench;

forming a first electrode in the active trench;

forming a second electrode disposed in the active trench below the first electrode; and

forming the first source region, having the first conductivity type, in the well region.

12. The method of claim 11, further comprising:

forming a third electrode in the charge control trench, the active trench including a different number of electrodes than the charge control trench.