Manufacturing method of power transistor device with super junction
First Claim
1. A method of manufacturing a power transistor device with a super junction, comprising:
- providing a substrate having a first conductivity type;
forming a first epitaxial layer on the substrate;
patterning the first epitaxial layer to form a plurality of trenches in the first epitaxial layer;
forming a second epitaxial layer on the first epitaxial layer and filling up the trenches with the second epitaxial layer, wherein the second epitaxial layer and the first epitaxial layer have different conductivity types;
patterning the second epitaxial layer to form a plurality of first through holes in the second epitaxial layer, wherein the through holes can expose the first epitaxial layer; and
forming a third epitaxial layer on the second epitaxial layer, wherein the third epitaxial layer fills up the first through holes and is in contact with the first epitaxial layer, and the third epitaxial layer and the first epitaxial layer have the same conductivity type, wherein the first epitaxial layer and the third epitaxial layer have different doping concentrations, and the first epitaxial layer and the third epitaxial layer have different widths in a direction parallel to a top surface of the substrate.
1 Assignment
0 Petitions
Accused Products
Abstract
The present invention provides a power transistor device with a super junction including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is disposed on the substrate, and has a plurality of trenches. The trenches are filled up with the second epitaxial layer, and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer. The second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer. The second epitaxial layer and the first epitaxial layer have different conductivity types. The through holes are filled up with the third epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer. The third epitaxial layer and the first epitaxial layer have the same conductivity type.
-
Citations
9 Claims
-
1. A method of manufacturing a power transistor device with a super junction, comprising:
-
providing a substrate having a first conductivity type; forming a first epitaxial layer on the substrate; patterning the first epitaxial layer to form a plurality of trenches in the first epitaxial layer; forming a second epitaxial layer on the first epitaxial layer and filling up the trenches with the second epitaxial layer, wherein the second epitaxial layer and the first epitaxial layer have different conductivity types; patterning the second epitaxial layer to form a plurality of first through holes in the second epitaxial layer, wherein the through holes can expose the first epitaxial layer; and forming a third epitaxial layer on the second epitaxial layer, wherein the third epitaxial layer fills up the first through holes and is in contact with the first epitaxial layer, and the third epitaxial layer and the first epitaxial layer have the same conductivity type, wherein the first epitaxial layer and the third epitaxial layer have different doping concentrations, and the first epitaxial layer and the third epitaxial layer have different widths in a direction parallel to a top surface of the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
Specification