Manufacturing method of power transistor device with super junction

• US 8,936,990 B2
• Filed: 07/04/2012
• Issued: 01/20/2015
• Est. Priority Date: 11/29/2011
• Status: Expired due to Fees

• Current Assignee: Anpec Electronics Corporation
• Original Assignee: Anpec Electronics Corporation
• Inventors: Lin, Yung-Fa, Hsu, Shou-Yi, Wu, Meng-Wei, Chang, Chia-Hao
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US13/541,763
• Publication Number:
  US 20130134487A1
• Time in Patent Office: 930 Days
• Field of Search: 438/301, 257/288, 257/E21.409, 257/E29.255
• US Class Current: 438/301
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

The present invention provides a power transistor device with a super junction including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is disposed on the substrate, and has a plurality of trenches. The trenches are filled up with the second epitaxial layer, and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer. The second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer. The second epitaxial layer and the first epitaxial layer have different conductivity types. The through holes are filled up with the third epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer. The third epitaxial layer and the first epitaxial layer have the same conductivity type.

Claims

1. A method of manufacturing a power transistor device with a super junction, comprising:

providing a substrate having a first conductivity type;

forming a first epitaxial layer on the substrate;

patterning the first epitaxial layer to form a plurality of trenches in the first epitaxial layer;

forming a second epitaxial layer on the first epitaxial layer and filling up the trenches with the second epitaxial layer, wherein the second epitaxial layer and the first epitaxial layer have different conductivity types;

patterning the second epitaxial layer to form a plurality of first through holes in the second epitaxial layer, wherein the through holes can expose the first epitaxial layer; and

forming a third epitaxial layer on the second epitaxial layer, wherein the third epitaxial layer fills up the first through holes and is in contact with the first epitaxial layer, and the third epitaxial layer and the first epitaxial layer have the same conductivity type, wherein the first epitaxial layer and the third epitaxial layer have different doping concentrations, and the first epitaxial layer and the third epitaxial layer have different widths in a direction parallel to a top surface of the substrate.

2. The method of manufacturing the power transistor device with the super junction according to claim 1, wherein the first epitaxial layer has a first conductivity type, and the second epitaxial layer has a second conductivity type different from the first conductivity type.

3. The method of manufacturing the power transistor device with the super junction according to claim 2, wherein after forming the third epitaxial layer, the method further comprises removing the third epitaxial layer on the second epitaxial layer so that a top surface of a third epitaxial layer is leveled with a top surface of the second epitaxial layer.

4. The method of manufacturing the power transistor device with the super junction according to claim 3, wherein after removing the third epitaxial layer on the second epitaxial layer, the method further comprises:

covering the second epitaxial layer and the third epitaxial layer with a fourth epitaxial layer having the first conductivity type;

forming at least a gate structure on the fourth epitaxial layer;

forming at least a doped body region having the second conductivity type in the fourth epitaxial layer, wherein the doped body region partially overlaps the gate structure and is in contact with the second epitaxial layer; and

forming at least a doped source region having the first conductivity type in the doped body region, wherein the doped source region partially overlaps the gate structure.

5. The method of manufacturing the power transistor device with the super junction according to claim 2, wherein after forming the third epitaxial layer, the method further comprises:

forming at least a gate structure on the third epitaxial layer; and

at least a doped body region having the second conductivity type disposed in the third epitaxial layer on one side of the gate structure and partially overlapped by the gate structure, wherein the doped body region is in contact with the second epitaxial layer.

6. The method of manufacturing the power transistor device with the super junction according to claim 2, further comprising repeating the steps of forming the second epitaxial layer, patterning the second epitaxial layer and forming the third epitaxial layer at least once, and forming at least a fifth epitaxial layer on the second epitaxial layer and forming at least a sixth epitaxial layer on the third epitaxial layer, wherein the fifth epitaxial layer has the second conductivity type and the sixth epitaxial layer has the first conductivity type.

7. The method of manufacturing the power transistor device with the super junction according to claim 1, wherein the first epitaxial layer has a second conductivity type different from the first conductivity type, and the second epitaxial layer has the first conductivity type.

8. The method of manufacturing the power transistor device with the super junction according to claim 7, wherein after forming the third epitaxial layer, the method further comprises patterning the third epitaxial layer to form a plurality of second through holes in the third epitaxial layer, wherein the second through holes expose the second epitaxial layer respectively.

9. The method of manufacturing the power transistor device with the super junction according to claim 8, wherein after patterning the third epitaxial layer, the method further comprises forming at least a fifth epitaxial layer on the second epitaxial layer exposed by the second through holes, wherein the fifth epitaxial layer has the first conductivity type.